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Commit 9aef85cc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (21 commits)
  drm: only trust core drm ioctls - driver ioctls are a mess.
  drm/i915: add support for Intel series 4 chipsets.
  drm/radeon: add hier-z registers for r300 and r500 chipsets
  drm/radeon: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT
  drm/radeon: switch IGP gart to use radeon_write_agp_base()
  drm/radeon: Restore sw interrupt on resume
  drm/r500: add support for AGP based cards.
  drm/radeon: fix texture uploads with large 3d textures (bug 13980)
  drm/radeon: add initial r500 support.
  drm/radeon: init pipe setup in kernel code.
  drm/radeon: fixup radeon_do_engine_reset
  drm/radeon: fix pixcache and purge/cache flushing registers
  drm/radeon: write AGP_BASE_2 on chips that support it.
  drm/radeon: merge IGP chip setup and fixup RS400 vs RS480 support
  drm/radeon: IGP clean up register and magic numbers.
  drm/rs690: set base 2 to 0.
  drm/rs690: set all of gart base address.
  radeon: add production microcode from AMD
  drm: pcigart use proper pci map interfaces.
  drm: the sg alloc ioctl should write back the handle to userspace
  ...
parents fdfe6d3d 858a3685

drivers/char/drm/ati_pcigart.c

+3 −5
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info 
		for (i = 0; i < pages; i++) {

			if (!entry->busaddr[i])

				break;

			pci_unmap_single(dev->pdev, entry->busaddr[i],

			pci_unmap_page(dev->pdev, entry->busaddr[i],

					 PAGE_SIZE, PCI_DMA_TODEVICE);

		}
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga 


	for (i = 0; i < pages; i++) {

		/* we need to support large memory configurations */

		entry->busaddr[i] = pci_map_single(dev->pdev,

						   page_address(entry->

								pagelist[i]),

						   PAGE_SIZE, PCI_DMA_TODEVICE);

		entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],

						 0, PAGE_SIZE, PCI_DMA_TODEVICE);

		if (entry->busaddr[i] == 0) {

			DRM_ERROR("unable to map PCIGART pages!\n");

			drm_ati_pcigart_cleanup(dev, gart_info);

drivers/char/drm/drm.h

+1 −1
Original line number Diff line number Diff line
@@ -628,7 +628,7 @@ struct drm_set_version { 
#define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, struct drm_agp_binding)

#define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, struct drm_agp_binding)



#define DRM_IOCTL_SG_ALLOC		DRM_IOW( 0x38, struct drm_scatter_gather)

#define DRM_IOCTL_SG_ALLOC		DRM_IOWR(0x38, struct drm_scatter_gather)

#define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, struct drm_scatter_gather)



#define DRM_IOCTL_WAIT_VBLANK		DRM_IOWR(0x3a, union drm_wait_vblank)

drivers/char/drm/drm_drv.c

+4 −3
Original line number Diff line number Diff line
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp, 
	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&

	    (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))

		ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];

	else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE))

	else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {

		ioctl = &drm_ioctls[nr];

	else

		cmd = ioctl->cmd;

	} else

		goto err_i1;



	/* Do not trust userspace, use our own definition */

	func = ioctl->func;

	/* is there a local override? */

	if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)

		func = dev->driver->dma_ioctl;





	if (!func) {

		DRM_DEBUG("no function\n");

		retcode = -EINVAL;

drivers/char/drm/drm_pciids.h

+9 −8
Original line number Diff line number Diff line
@@ -103,20 +103,18 @@ 
	{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \

	{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \

	{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \

	{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -411,4 +409,7 @@ 
	{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0, 0, 0}

drivers/char/drm/i915_drv.h

+9 −2
Original line number Diff line number Diff line
@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
		       (dev)->pci_device == 0x29A2 || \

		       (dev)->pci_device == 0x2A02 || \

		       (dev)->pci_device == 0x2A12 || \

		       (dev)->pci_device == 0x2A42)

		       (dev)->pci_device == 0x2A42 || \

		       (dev)->pci_device == 0x2E02 || \

		       (dev)->pci_device == 0x2E12 || \

		       (dev)->pci_device == 0x2E22)



#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)



#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)



#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \

		     (dev)->pci_device == 0x2E12 || \

		     (dev)->pci_device == 0x2E22)



#define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||	\

			(dev)->pci_device == 0x29B2 ||	\

			(dev)->pci_device == 0x29D2)
@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \

			IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))



#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev))

#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))



#define PRIMARY_RINGBUFFER_SIZE         (128*1024)