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Commit 9a6edc3a authored by Ilia Mirkin's avatar Ilia Mirkin Committed by Ben Skeggs
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drm/nouveau/kms/nv04-nv40: improve overlay error detection, fix pitch setting 



We were previously setting the pitch based on a perfectly packed buffer.
This does not necessarily happen. Either modetest started generating
such buffers recently, or earlier testing only happened with well-picked
overlay sizes.

While we're at it, beef up and refactor the error state detection.

Signed-off-by: default avatarIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 3ce72bcf

drivers/gpu/drm/nouveau/dispnv04/overlay.c

+34 −28
Original line number Diff line number Diff line
@@ -89,6 +89,26 @@ cos_mul(int degrees, int factor) 
	return sin_mul((degrees + 90) % 360, factor);

}



static int

verify_scaling(const struct drm_framebuffer *fb, uint8_t shift,

               uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,

               uint32_t crtc_w, uint32_t crtc_h)

{

	if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) {

		DRM_DEBUG_KMS("Unsuitable framebuffer scaling: %dx%d -> %dx%d\n",

			      src_w, src_h, crtc_w, crtc_h);

		return -ERANGE;

	}



	if (src_x != 0 || src_y != 0) {

		DRM_DEBUG_KMS("Unsuitable framebuffer offset: %d,%d\n",

                              src_x, src_y);

		return -ERANGE;

	}



	return 0;

}



static int

nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,

		  struct drm_framebuffer *fb, int crtc_x, int crtc_y,
@@ -107,7 +127,9 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	bool flip = nv_plane->flip;

	int soff = NV_PCRTC0_SIZE * nv_crtc->index;

	int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;

	int format, ret;

	unsigned shift = drm->client.device.info.chipset >= 0x30 ? 1 : 3;

	unsigned format = 0;

	int ret;



	/* Source parameters given in 16.16 fixed point, ignore fractional. */

	src_x >>= 16;
@@ -115,18 +137,9 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	src_w >>= 16;

	src_h >>= 16;



	format = ALIGN(src_w * 4, 0x100);



	if (format > 0xffff)

		return -ERANGE;



	if (drm->client.device.info.chipset >= 0x30) {

		if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))

			return -ERANGE;

	} else {

		if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3))

			return -ERANGE;

	}

	ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h);

	if (ret)

		return ret;



	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);

	if (ret)
@@ -160,7 +173,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
		nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),

			nv_fb->nvbo->bo.offset + fb->offsets[1]);

	}

	nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format);

	nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]);

	nvif_wr32(dev, NV_PVIDEO_STOP, 0);

	/* TODO: wait for vblank? */

	nvif_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1);
@@ -357,7 +370,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	struct nouveau_bo *cur = nv_plane->cur;

	uint32_t overlay = 1;

	int brightness = (nv_plane->brightness - 512) * 62 / 512;

	int pitch, ret, i;

	int ret, i;



	/* Source parameters given in 16.16 fixed point, ignore fractional. */

	src_x >>= 16;
@@ -365,17 +378,9 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	src_w >>= 16;

	src_h >>= 16;



	pitch = ALIGN(src_w * 4, 0x100);



	if (pitch > 0xffff)

		return -ERANGE;



	/* TODO: Compute an offset? Not sure how to do this for YUYV. */

	if (src_x != 0 || src_y != 0)

		return -ERANGE;



	if (crtc_w < src_w || crtc_h < src_h)

		return -ERANGE;

	ret = verify_scaling(fb, 0, src_x, src_y, src_w, src_h, crtc_w, crtc_h);

	if (ret)

		return ret;



	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);

	if (ret)
@@ -390,7 +395,8 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	for (i = 0; i < 2; i++) {

		nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,

			  nv_fb->nvbo->bo.offset);

		nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch);

		nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i,

			  fb->pitches[0]);

		nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);

	}

	nvif_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x);