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Commit 97dcb82d authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
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[MIPS] Define MIPS_CPU_IRQ_BASE in generic header 



The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b6ec8f06

arch/mips/basler/excite/excite_irq.c

+3 −3
Original line number Diff line number Diff line
@@ -47,9 +47,9 @@ extern asmlinkage void excite_handle_int(void); 
 */

void __init arch_init_irq(void)

{

	mips_cpu_irq_init(0);

	rm7k_cpu_irq_init(8);

	rm9k_cpu_irq_init(12);

	mips_cpu_irq_init();

	rm7k_cpu_irq_init();

	rm9k_cpu_irq_init();



#ifdef CONFIG_KGDB

	excite_kgdb_init();

arch/mips/cobalt/irq.c

+1 −1
Original line number Diff line number Diff line
@@ -104,7 +104,7 @@ void __init arch_init_irq(void) 
	GT_WRITE(GT_INTRMASK_OFS, 0);



	init_i8259_irqs();				/*  0 ... 15 */

	mips_cpu_irq_init(COBALT_CPU_IRQ);		/* 16 ... 23 */

	mips_cpu_irq_init();		/* 16 ... 23 */



	/*

	 * Mask all cpu interrupts

arch/mips/ddb5xxx/ddb5477/irq.c

+2 −2
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <linux/ptrace.h>



#include <asm/i8259.h>

#include <asm/irq_cpu.h>

#include <asm/system.h>

#include <asm/mipsregs.h>

#include <asm/debug.h>
@@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) 
}



extern void vrc5477_irq_init(u32 base);

extern void mips_cpu_irq_init(u32 base);

static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };



void __init arch_init_irq(void)
@@ -125,7 +125,7 @@ void __init arch_init_irq(void) 


	/* init all controllers */

	init_i8259_irqs();

	mips_cpu_irq_init(CPU_IRQ_BASE);

	mips_cpu_irq_init();

	vrc5477_irq_init(VRC5477_IRQ_BASE);

arch/mips/dec/setup.c

+6 −6
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ static void __init dec_init_kn01(void) 
	memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,

		sizeof(kn01_cpu_mask_nr_tbl));



	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

	mips_cpu_irq_init();



}				/* dec_init_kn01 */
@@ -309,7 +309,7 @@ static void __init dec_init_kn230(void) 
	memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,

		sizeof(kn230_cpu_mask_nr_tbl));



	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

	mips_cpu_irq_init();



}				/* dec_init_kn230 */
@@ -403,7 +403,7 @@ static void __init dec_init_kn02(void) 
	memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,

		sizeof(kn02_asic_mask_nr_tbl));



	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

	mips_cpu_irq_init();

	init_kn02_irqs(KN02_IRQ_BASE);



}				/* dec_init_kn02 */
@@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void) 
	memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,

		sizeof(kn02ba_asic_mask_nr_tbl));



	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

	mips_cpu_irq_init();

	init_ioasic_irqs(IO_IRQ_BASE);



}				/* dec_init_kn02ba */
@@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void) 
	memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,

		sizeof(kn02ca_asic_mask_nr_tbl));



	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

	mips_cpu_irq_init();

	init_ioasic_irqs(IO_IRQ_BASE);



}				/* dec_init_kn02ca */
@@ -702,7 +702,7 @@ static void __init dec_init_kn03(void) 
	memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,

		sizeof(kn03_asic_mask_nr_tbl));



	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

	mips_cpu_irq_init();

	init_ioasic_irqs(IO_IRQ_BASE);



}				/* dec_init_kn03 */

arch/mips/emma2rh/markeins/irq.c

+1 −1
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ void __init arch_init_irq(void) 
	emma2rh_irq_init(EMMA2RH_IRQ_BASE);

	emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);

	emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);

	mips_cpu_irq_init(CPU_IRQ_BASE);

	mips_cpu_irq_init();



	/* setup cascade interrupts */

	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);