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Commit 93ffbe8e authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Chris Wilson
Browse files

drm/i915/guc: Introduce USES_GUC_xxx helper macros 



In the upcoming patch we will change the way how to recognize
when GuC is in use. Using helper macros will minimize scope
of that changes. While here, update dev_info message.

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-3-michal.wajdeczko@intel.com
parent 0dd940c8

drivers/gpu/drm/i915/i915_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -3239,6 +3239,10 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))

#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))



/* Having a GuC is not the same as using a GuC */

#define USES_GUC(dev_priv)		(i915_modparams.enable_guc_loading)

#define USES_GUC_SUBMISSION(dev_priv)	(i915_modparams.enable_guc_submission)



#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)



#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)

drivers/gpu/drm/i915/i915_gem_context.c

+2 −2
Original line number Diff line number Diff line
@@ -316,7 +316,7 @@ __create_hw_context(struct drm_i915_private *dev_priv, 
	 * present or not in use we still need a small bias as ring wraparound

	 * at offset 0 sometimes hangs. No idea why.

	 */

	if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)

	if (USES_GUC(dev_priv))

		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;

	else

		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
@@ -409,7 +409,7 @@ i915_gem_context_create_gvt(struct drm_device *dev) 
	i915_gem_context_set_closed(ctx); /* not user accessible */

	i915_gem_context_clear_bannable(ctx);

	i915_gem_context_set_force_single_submission(ctx);

	if (!i915_modparams.enable_guc_submission)

	if (!USES_GUC_SUBMISSION(to_i915(dev)))

		ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */



	GEM_BUG_ON(i915_gem_context_is_kernel(ctx));

drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -3503,7 +3503,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) 
	 * currently don't have any bits spare to pass in this upper

	 * restriction!

	 */

	if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {

	if (USES_GUC(dev_priv)) {

		ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);

		ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);

	}

drivers/gpu/drm/i915/i915_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -1400,7 +1400,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) 


	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {

		notify_ring(engine);

		tasklet |= i915_modparams.enable_guc_submission;

		tasklet |= USES_GUC_SUBMISSION(engine->i915);

	}



	if (tasklet)

drivers/gpu/drm/i915/intel_guc.c

+1 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ void intel_guc_init_params(struct intel_guc *guc) 
	}



	/* If GuC submission is enabled, set up additional parameters here */

	if (i915_modparams.enable_guc_submission) {

	if (USES_GUC_SUBMISSION(dev_priv)) {

		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;

		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);

		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;