Commit 90019f8f authored Sep 05, 2017 by Paul Burton Committed by Marc Zyngier Sep 19, 2017

irqchip.mips-gic: Fix shared interrupt mask writes



The write_gic_smask() & write_gic_rmask() functions take a shared
interrupt number as a parameter, but we're incorrectly providing them a
bitmask with the shared interrupt's bit set. This effectively means that
we mask or unmask the shared interrupt 1<<n rather than shared interrupt
n, and as a result likely drop interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 68898c8765f4 ("irqchip: mips-gic: Drop gic_(re)set_mask() functions")
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

parent 6c09ffd0

drivers/irqchip/irq-mips-gic.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -169,7 +169,7 @@ static void gic_mask_irq(struct irq_data *d)
		{
		unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);

		write_gic_rmask(BIT(intr));
		write_gic_rmask(intr);
		gic_clear_pcpu_masks(intr);
		}

		@@ -179,7 +179,7 @@ static void gic_unmask_irq(struct irq_data *d)
		unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
		unsigned int cpu;

		write_gic_smask(BIT(intr));
		write_gic_smask(intr);

		gic_clear_pcpu_masks(intr);
		cpu = cpumask_first_and(affinity, cpu_online_mask);
		@@ -767,7 +767,7 @@ static int __init gic_of_init(struct device_node *node,
		for (i = 0; i < gic_shared_intrs; i++) {
		change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
		change_gic_trig(i, GIC_TRIG_LEVEL);
		write_gic_rmask(BIT(i));
		write_gic_rmask(i);
		}

		for (i = 0; i < gic_vpes; i++) {