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Commit 8ea658ce authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
1GbE Intel Wired LAN Driver Updates 2016-05-13

This series contains updates to e1000e, igb and igbvf.

Steve Shih fixes an issue for disabling auto-negotiation and forcing
speed and duplex settings for non-copper media.

Brian Walsh cleanups some inconsistency in the use of return variables
names to avoid confusion.

Jake cleans up the drivers to use the BIT() macro when it can, which will
future proof the drivers for GCC 6 when it gets released.  Cleaned up
dead code which was never being used.  Also fixed e1000e, where it was
incorrectly restting the SYSTIM registers every time the ioctl was being
run.

Denys Vlasenko fixes an oversight where incvalue variable holds a 32
bit value so we should declare it as such, instead of 64 bits.  Also
fixed an overflow check, where two reads are the same, then it is not
an overflow.

Nathan Sullivan fixes the PTP timestamps for transmit and receive
latency based on the current link speed.

Alexander Duyck adds support for partial GSO segmentation in the case
of tunnels for igb and igbvf.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ed7cbbce aa524b66

drivers/net/ethernet/intel/e1000e/80003es2lan.c

+6 −6
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 
	/* EEPROM access above 16k is unsupported */

	if (size > 14)

		size = 14;

	nvm->word_size = 1 << size;

	nvm->word_size = BIT(size);



	return 0;

}
@@ -845,27 +845,27 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 


	/* Transmit Descriptor Control 0 */

	reg = er32(TXDCTL(0));

	reg |= (1 << 22);

	reg |= BIT(22);

	ew32(TXDCTL(0), reg);



	/* Transmit Descriptor Control 1 */

	reg = er32(TXDCTL(1));

	reg |= (1 << 22);

	reg |= BIT(22);

	ew32(TXDCTL(1), reg);



	/* Transmit Arbitration Control 0 */

	reg = er32(TARC(0));

	reg &= ~(0xF << 27);	/* 30:27 */

	if (hw->phy.media_type != e1000_media_type_copper)

		reg &= ~(1 << 20);

		reg &= ~BIT(20);

	ew32(TARC(0), reg);



	/* Transmit Arbitration Control 1 */

	reg = er32(TARC(1));

	if (er32(TCTL) & E1000_TCTL_MULR)

		reg &= ~(1 << 28);

		reg &= ~BIT(28);

	else

		reg |= (1 << 28);

		reg |= BIT(28);

	ew32(TARC(1), reg);



	/* Disable IPv6 extension header parsing because some malformed

drivers/net/ethernet/intel/e1000e/82571.c

+15 −15
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 
		/* EEPROM access above 16k is unsupported */

		if (size > 14)

			size = 14;

		nvm->word_size = 1 << size;

		nvm->word_size = BIT(size);

		break;

	}
@@ -1163,12 +1163,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 


	/* Transmit Descriptor Control 0 */

	reg = er32(TXDCTL(0));

	reg |= (1 << 22);

	reg |= BIT(22);

	ew32(TXDCTL(0), reg);



	/* Transmit Descriptor Control 1 */

	reg = er32(TXDCTL(1));

	reg |= (1 << 22);

	reg |= BIT(22);

	ew32(TXDCTL(1), reg);



	/* Transmit Arbitration Control 0 */
@@ -1177,11 +1177,11 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);

		reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);

		break;

	case e1000_82574:

	case e1000_82583:

		reg |= (1 << 26);

		reg |= BIT(26);

		break;

	default:

		break;
@@ -1193,12 +1193,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		reg &= ~((1 << 29) | (1 << 30));

		reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);

		reg &= ~(BIT(29) | BIT(30));

		reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);

		if (er32(TCTL) & E1000_TCTL_MULR)

			reg &= ~(1 << 28);

			reg &= ~BIT(28);

		else

			reg |= (1 << 28);

			reg |= BIT(28);

		ew32(TARC(1), reg);

		break;

	default:
@@ -1211,7 +1211,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
	case e1000_82574:

	case e1000_82583:

		reg = er32(CTRL);

		reg &= ~(1 << 29);

		reg &= ~BIT(29);

		ew32(CTRL, reg);

		break;

	default:
@@ -1224,8 +1224,8 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
	case e1000_82574:

	case e1000_82583:

		reg = er32(CTRL_EXT);

		reg &= ~(1 << 23);

		reg |= (1 << 22);

		reg &= ~BIT(23);

		reg |= BIT(22);

		ew32(CTRL_EXT, reg);

		break;

	default:
@@ -1261,7 +1261,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
	case e1000_82574:

	case e1000_82583:

		reg = er32(GCR);

		reg |= (1 << 22);

		reg |= BIT(22);

		ew32(GCR, reg);



		/* Workaround for hardware errata.
@@ -1308,7 +1308,7 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw) 
				       E1000_VFTA_ENTRY_SHIFT) &

			    E1000_VFTA_ENTRY_MASK;

			vfta_bit_in_reg =

			    1 << (hw->mng_cookie.vlan_id &

			    BIT(hw->mng_cookie.vlan_id &

				E1000_VFTA_ENTRY_BIT_SHIFT_MASK);

		}

		break;

drivers/net/ethernet/intel/e1000e/e1000.h

+55 −54
Original line number Diff line number Diff line
@@ -109,18 +109,18 @@ struct e1000_info; 
#define E1000_TXDCTL_DMA_BURST_ENABLE                          \

	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \

	 E1000_TXDCTL_COUNT_DESC |                             \

	 (1 << 16) | /* wthresh must be +1 more than desired */\

	 (1 << 8)  | /* hthresh */                             \

	 (1u << 16) | /* wthresh must be +1 more than desired */\

	 (1u << 8)  | /* hthresh */                             \

	 0x1f)        /* pthresh */



#define E1000_RXDCTL_DMA_BURST_ENABLE                          \

	(0x01000000 | /* set descriptor granularity */         \

	 (4 << 16)  | /* set writeback threshold    */         \

	 (4 << 8)   | /* set prefetch threshold     */         \

	 (4u << 16) | /* set writeback threshold    */         \

	 (4u << 8)  | /* set prefetch threshold     */         \

	 0x20)        /* set hthresh                */



#define E1000_TIDV_FPD (1 << 31)

#define E1000_RDTR_FPD (1 << 31)

#define E1000_TIDV_FPD BIT(31)

#define E1000_RDTR_FPD BIT(31)



enum e1000_boards {

	board_82571,
@@ -347,6 +347,7 @@ struct e1000_adapter { 
	struct ptp_clock *ptp_clock;

	struct ptp_clock_info ptp_clock_info;

	struct pm_qos_request pm_qos_req;

	s32 ptp_delta;



	u16 eee_advert;

};
@@ -404,53 +405,53 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 
#define E1000_82574_SYSTIM_EPSILON	(1ULL << 35ULL)



/* hardware capability, feature, and workaround flags */

#define FLAG_HAS_AMT                      (1 << 0)

#define FLAG_HAS_FLASH                    (1 << 1)

#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)

#define FLAG_HAS_WOL                      (1 << 3)

/* reserved bit4 */

#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)

#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)

#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)

#define FLAG_READ_ONLY_NVM                (1 << 8)

#define FLAG_IS_ICH                       (1 << 9)

#define FLAG_HAS_MSIX                     (1 << 10)

#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)

#define FLAG_IS_QUAD_PORT_A               (1 << 12)

#define FLAG_IS_QUAD_PORT                 (1 << 13)

#define FLAG_HAS_HW_TIMESTAMP             (1 << 14)

#define FLAG_APME_IN_WUC                  (1 << 15)

#define FLAG_APME_IN_CTRL3                (1 << 16)

#define FLAG_APME_CHECK_PORT_B            (1 << 17)

#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)

#define FLAG_NO_WAKE_UCAST                (1 << 19)

#define FLAG_MNG_PT_ENABLED               (1 << 20)

#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)

#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)

#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)

#define FLAG_RX_NEEDS_RESTART             (1 << 24)

#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)

#define FLAG_SMART_POWER_DOWN             (1 << 26)

#define FLAG_MSI_ENABLED                  (1 << 27)

/* reserved (1 << 28) */

#define FLAG_TSO_FORCE                    (1 << 29)

#define FLAG_RESTART_NOW                  (1 << 30)

#define FLAG_MSI_TEST_FAILED              (1 << 31)



#define FLAG2_CRC_STRIPPING               (1 << 0)

#define FLAG2_HAS_PHY_WAKEUP              (1 << 1)

#define FLAG2_IS_DISCARDING               (1 << 2)

#define FLAG2_DISABLE_ASPM_L1             (1 << 3)

#define FLAG2_HAS_PHY_STATS               (1 << 4)

#define FLAG2_HAS_EEE                     (1 << 5)

#define FLAG2_DMA_BURST                   (1 << 6)

#define FLAG2_DISABLE_ASPM_L0S            (1 << 7)

#define FLAG2_DISABLE_AIM                 (1 << 8)

#define FLAG2_CHECK_PHY_HANG              (1 << 9)

#define FLAG2_NO_DISABLE_RX               (1 << 10)

#define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)

#define FLAG2_DFLT_CRC_STRIPPING          (1 << 12)

#define FLAG2_CHECK_RX_HWTSTAMP           (1 << 13)

#define FLAG_HAS_AMT                      BIT(0)

#define FLAG_HAS_FLASH                    BIT(1)

#define FLAG_HAS_HW_VLAN_FILTER           BIT(2)

#define FLAG_HAS_WOL                      BIT(3)

/* reserved BIT(4) */

#define FLAG_HAS_CTRLEXT_ON_LOAD          BIT(5)

#define FLAG_HAS_SWSM_ON_LOAD             BIT(6)

#define FLAG_HAS_JUMBO_FRAMES             BIT(7)

#define FLAG_READ_ONLY_NVM                BIT(8)

#define FLAG_IS_ICH                       BIT(9)

#define FLAG_HAS_MSIX                     BIT(10)

#define FLAG_HAS_SMART_POWER_DOWN         BIT(11)

#define FLAG_IS_QUAD_PORT_A               BIT(12)

#define FLAG_IS_QUAD_PORT                 BIT(13)

#define FLAG_HAS_HW_TIMESTAMP             BIT(14)

#define FLAG_APME_IN_WUC                  BIT(15)

#define FLAG_APME_IN_CTRL3                BIT(16)

#define FLAG_APME_CHECK_PORT_B            BIT(17)

#define FLAG_DISABLE_FC_PAUSE_TIME        BIT(18)

#define FLAG_NO_WAKE_UCAST                BIT(19)

#define FLAG_MNG_PT_ENABLED               BIT(20)

#define FLAG_RESET_OVERWRITES_LAA         BIT(21)

#define FLAG_TARC_SPEED_MODE_BIT          BIT(22)

#define FLAG_TARC_SET_BIT_ZERO            BIT(23)

#define FLAG_RX_NEEDS_RESTART             BIT(24)

#define FLAG_LSC_GIG_SPEED_DROP           BIT(25)

#define FLAG_SMART_POWER_DOWN             BIT(26)

#define FLAG_MSI_ENABLED                  BIT(27)

/* reserved BIT(28) */

#define FLAG_TSO_FORCE                    BIT(29)

#define FLAG_RESTART_NOW                  BIT(30)

#define FLAG_MSI_TEST_FAILED              BIT(31)



#define FLAG2_CRC_STRIPPING               BIT(0)

#define FLAG2_HAS_PHY_WAKEUP              BIT(1)

#define FLAG2_IS_DISCARDING               BIT(2)

#define FLAG2_DISABLE_ASPM_L1             BIT(3)

#define FLAG2_HAS_PHY_STATS               BIT(4)

#define FLAG2_HAS_EEE                     BIT(5)

#define FLAG2_DMA_BURST                   BIT(6)

#define FLAG2_DISABLE_ASPM_L0S            BIT(7)

#define FLAG2_DISABLE_AIM                 BIT(8)

#define FLAG2_CHECK_PHY_HANG              BIT(9)

#define FLAG2_NO_DISABLE_RX               BIT(10)

#define FLAG2_PCIM2PCI_ARBITER_WA         BIT(11)

#define FLAG2_DFLT_CRC_STRIPPING          BIT(12)

#define FLAG2_CHECK_RX_HWTSTAMP           BIT(13)



#define E1000_RX_DESC_PS(R, i)	    \

	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))

drivers/net/ethernet/intel/e1000e/ethtool.c

+33 −24
Original line number Diff line number Diff line
@@ -201,6 +201,9 @@ static int e1000_get_settings(struct net_device *netdev, 
	else

		ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;



	if (hw->phy.media_type != e1000_media_type_copper)

		ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_INVALID;



	return 0;

}
@@ -236,8 +239,13 @@ static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx) 
		mac->forced_speed_duplex = ADVERTISE_100_FULL;

		break;

	case SPEED_1000 + DUPLEX_FULL:

		if (adapter->hw.phy.media_type == e1000_media_type_copper) {

			mac->autoneg = 1;

		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;

			adapter->hw.phy.autoneg_advertised =

				ADVERTISE_1000_FULL;

		} else {

			mac->forced_speed_duplex = ADVERTISE_1000_FULL;

		}

		break;

	case SPEED_1000 + DUPLEX_HALF:	/* not supported */

	default:
@@ -439,7 +447,8 @@ static void e1000_get_regs(struct net_device *netdev, 


	memset(p, 0, E1000_REGS_LEN * sizeof(u32));



	regs->version = (1 << 24) | (adapter->pdev->revision << 16) |

	regs->version = (1u << 24) |

			(adapter->pdev->revision << 16) |

			adapter->pdev->device;



	regs_buff[0] = er32(CTRL);
@@ -895,7 +904,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) 
	case e1000_pch2lan:

	case e1000_pch_lpt:

	case e1000_pch_spt:

		mask |= (1 << 18);

		mask |= BIT(18);

		break;

	default:

		break;
@@ -914,9 +923,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) 


			/* SHRAH[9] different than the others */

			if (i == 10)

				mask |= (1 << 30);

				mask |= BIT(30);

			else

				mask &= ~(1 << 30);

				mask &= ~BIT(30);

		}

		if (mac->type == e1000_pch2lan) {

			/* SHRAH[0,1,2] different than previous */
@@ -924,7 +933,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) 
				mask &= 0xFFF4FFFF;

			/* SHRAH[3] different than SHRAH[0,1,2] */

			if (i == 4)

				mask |= (1 << 30);

				mask |= BIT(30);

			/* RAR[1-6] owned by management engine - skipping */

			if (i > 0)

				i += 6;
@@ -1019,7 +1028,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) 
	/* Test each interrupt */

	for (i = 0; i < 10; i++) {

		/* Interrupt to test */

		mask = 1 << i;

		mask = BIT(i);



		if (adapter->flags & FLAG_IS_ICH) {

			switch (mask) {
@@ -1387,7 +1396,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 
	case e1000_phy_82579:

		/* Disable PHY energy detect power down */

		e1e_rphy(hw, PHY_REG(0, 21), &phy_reg);

		e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~(1 << 3));

		e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3));

		/* Disable full chip energy detect */

		e1e_rphy(hw, PHY_REG(776, 18), &phy_reg);

		e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1);
@@ -1453,7 +1462,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter) 


	/* disable autoneg */

	ctrl = er32(TXCW);

	ctrl &= ~(1 << 31);

	ctrl &= ~BIT(31);

	ew32(TXCW, ctrl);



	link = (er32(STATUS) & E1000_STATUS_LU);
@@ -2283,19 +2292,19 @@ static int e1000e_get_ts_info(struct net_device *netdev, 
				  SOF_TIMESTAMPING_RX_HARDWARE |

				  SOF_TIMESTAMPING_RAW_HARDWARE);



	info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);



	info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |

			    (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |

			    (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |

			    (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |

			    (1 << HWTSTAMP_FILTER_ALL));

	info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);



	info->rx_filters = (BIT(HWTSTAMP_FILTER_NONE) |

			    BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |

			    BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |

			    BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |

			    BIT(HWTSTAMP_FILTER_ALL));



	if (adapter->ptp_clock)

		info->phc_index = ptp_clock_index(adapter->ptp_clock);

drivers/net/ethernet/intel/e1000e/ich8lan.c

+22 −22
Original line number Diff line number Diff line
@@ -1048,7 +1048,7 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 


		while (value > PCI_LTR_VALUE_MASK) {

			scale++;

			value = DIV_ROUND_UP(value, (1 << 5));

			value = DIV_ROUND_UP(value, BIT(5));

		}

		if (scale > E1000_LTRV_SCALE_MAX) {

			e_dbg("Invalid LTR latency scale %d\n", scale);
@@ -1573,7 +1573,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 
		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;



		if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)

			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);

			phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);



		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);

		break;
@@ -2044,9 +2044,9 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 
		/* Restore SMBus frequency */

		if (freq--) {

			phy_data &= ~HV_SMB_ADDR_FREQ_MASK;

			phy_data |= (freq & (1 << 0)) <<

			phy_data |= (freq & BIT(0)) <<

			    HV_SMB_ADDR_FREQ_LOW_SHIFT;

			phy_data |= (freq & (1 << 1)) <<

			phy_data |= (freq & BIT(1)) <<

			    (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);

		} else {

			e_dbg("Unsupported SMB frequency in PHY\n");
@@ -2530,7 +2530,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 


	/* disable Rx path while enabling/disabling workaround */

	e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);

	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));

	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));

	if (ret_val)

		return ret_val;
@@ -2561,7 +2561,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 


		/* Enable jumbo frame workaround in the MAC */

		mac_reg = er32(FFLT_DBG);

		mac_reg &= ~(1 << 14);

		mac_reg &= ~BIT(14);

		mac_reg |= (7 << 15);

		ew32(FFLT_DBG, mac_reg);
@@ -2576,7 +2576,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
			return ret_val;

		ret_val = e1000e_write_kmrn_reg(hw,

						E1000_KMRNCTRLSTA_CTRL_OFFSET,

						data | (1 << 0));

						data | BIT(0));

		if (ret_val)

			return ret_val;

		ret_val = e1000e_read_kmrn_reg(hw,
@@ -2600,7 +2600,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
		if (ret_val)

			return ret_val;

		e1e_rphy(hw, PHY_REG(769, 16), &data);

		data &= ~(1 << 13);

		data &= ~BIT(13);

		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);

		if (ret_val)

			return ret_val;
@@ -2614,7 +2614,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
		if (ret_val)

			return ret_val;

		e1e_rphy(hw, HV_PM_CTRL, &data);

		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));

		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));

		if (ret_val)

			return ret_val;

	} else {
@@ -2634,7 +2634,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
			return ret_val;

		ret_val = e1000e_write_kmrn_reg(hw,

						E1000_KMRNCTRLSTA_CTRL_OFFSET,

						data & ~(1 << 0));

						data & ~BIT(0));

		if (ret_val)

			return ret_val;

		ret_val = e1000e_read_kmrn_reg(hw,
@@ -2657,7 +2657,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
		if (ret_val)

			return ret_val;

		e1e_rphy(hw, PHY_REG(769, 16), &data);

		data |= (1 << 13);

		data |= BIT(13);

		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);

		if (ret_val)

			return ret_val;
@@ -2671,13 +2671,13 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
		if (ret_val)

			return ret_val;

		e1e_rphy(hw, HV_PM_CTRL, &data);

		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));

		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));

		if (ret_val)

			return ret_val;

	}



	/* re-enable Rx path after enabling/disabling workaround */

	return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));

	return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));

}



/**
@@ -4841,7 +4841,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 


	/* Extended Device Control */

	reg = er32(CTRL_EXT);

	reg |= (1 << 22);

	reg |= BIT(22);

	/* Enable PHY low-power state when MAC is at D3 w/o WoL */

	if (hw->mac.type >= e1000_pchlan)

		reg |= E1000_CTRL_EXT_PHYPDEN;
@@ -4849,34 +4849,34 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 


	/* Transmit Descriptor Control 0 */

	reg = er32(TXDCTL(0));

	reg |= (1 << 22);

	reg |= BIT(22);

	ew32(TXDCTL(0), reg);



	/* Transmit Descriptor Control 1 */

	reg = er32(TXDCTL(1));

	reg |= (1 << 22);

	reg |= BIT(22);

	ew32(TXDCTL(1), reg);



	/* Transmit Arbitration Control 0 */

	reg = er32(TARC(0));

	if (hw->mac.type == e1000_ich8lan)

		reg |= (1 << 28) | (1 << 29);

	reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);

		reg |= BIT(28) | BIT(29);

	reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);

	ew32(TARC(0), reg);



	/* Transmit Arbitration Control 1 */

	reg = er32(TARC(1));

	if (er32(TCTL) & E1000_TCTL_MULR)

		reg &= ~(1 << 28);

		reg &= ~BIT(28);

	else

		reg |= (1 << 28);

	reg |= (1 << 24) | (1 << 26) | (1 << 30);

		reg |= BIT(28);

	reg |= BIT(24) | BIT(26) | BIT(30);

	ew32(TARC(1), reg);



	/* Device Status */

	if (hw->mac.type == e1000_ich8lan) {

		reg = er32(STATUS);

		reg &= ~(1 << 31);

		reg &= ~BIT(31);

		ew32(STATUS, reg);

	}