Merge branch 'topic/hda-cleanup' into for-next

		return 0;

	trace_hda_unsol_event(bus, res, res_ex);

	unsol = bus->unsol;

	if (!unsol)

		return 0;

	unsol = &bus->unsol;

	wp = (unsol->wp + 1) % HDA_UNSOL_QUEUE_SIZE;

	unsol->wp = wp;

 */

static void process_unsol_events(struct work_struct *work)

{

	struct hda_bus_unsolicited *unsol =

		container_of(work, struct hda_bus_unsolicited, work);

	struct hda_bus *bus = unsol->bus;

	struct hda_bus *bus = container_of(work, struct hda_bus, unsol.work);

	struct hda_bus_unsolicited *unsol = &bus->unsol;

	struct hda_codec *codec;

	unsigned int rp, caddr, res;

	}

}

/*

 * initialize unsolicited queue

 */

static int init_unsol_queue(struct hda_bus *bus)

{

	struct hda_bus_unsolicited *unsol;

	if (bus->unsol) /* already initialized */

		return 0;

	unsol = kzalloc(sizeof(*unsol), GFP_KERNEL);

	if (!unsol) {

		dev_err(bus->card->dev, "can't allocate unsolicited queue\n");

		return -ENOMEM;

	}

	INIT_WORK(&unsol->work, process_unsol_events);

	unsol->bus = bus;

	bus->unsol = unsol;

	return 0;

}

/*

 * destructor

 */

	WARN_ON(!list_empty(&bus->codec_list));

	if (bus->workq)

		flush_workqueue(bus->workq);

	kfree(bus->unsol);

	if (bus->ops.private_free)

		bus->ops.private_free(bus);

	if (bus->workq)

/**

 * snd_hda_bus_new - create a HDA bus

 * @card: the card entry

 * @temp: the template for hda_bus information

 * @busp: the pointer to store the created bus instance

 *

 * Returns 0 if successful, or a negative error code.

 */

int snd_hda_bus_new(struct snd_card *card,

			      const struct hda_bus_template *temp,

		    struct hda_bus **busp)

{

	struct hda_bus *bus;

		.dev_free = snd_hda_bus_dev_free,

	};

	if (snd_BUG_ON(!temp))

		return -EINVAL;

	if (snd_BUG_ON(!temp->ops.command || !temp->ops.get_response))

		return -EINVAL;

	if (busp)

		*busp = NULL;

	}

	bus->card = card;

	bus->private_data = temp->private_data;

	bus->pci = temp->pci;

	bus->modelname = temp->modelname;

	bus->power_save = temp->power_save;

	bus->ops = temp->ops;

	mutex_init(&bus->cmd_mutex);

	mutex_init(&bus->prepare_mutex);

	INIT_LIST_HEAD(&bus->codec_list);

	INIT_WORK(&bus->unsol.work, process_unsol_events);

	snprintf(bus->workq_name, sizeof(bus->workq_name),

		 "hd-audio%d", card->number);

		return err;

	}

	if (codec->patch_ops.unsol_event) {

		err = init_unsol_queue(codec->bus);

		if (err < 0)

			return err;

	}

	/* audio codec should override the mixer name */

	if (codec->afg || !*codec->bus->card->mixername)

		snprintf(codec->bus->card->mixername,

static int codec_amp_update(struct hda_codec *codec, hda_nid_t nid, int ch,

			    int direction, int idx, int mask, int val,

			    bool init_only)

			    bool init_only, bool cache_only)

{

	struct hda_amp_info *info;

	unsigned int caps;

	unsigned int cache_only;

	if (snd_BUG_ON(mask & ~0xff))

		mask &= 0xff;

		return 0;

	}

	info->vol[ch] = val;

	cache_only = info->head.dirty = codec->cached_write;

	info->head.dirty |= cache_only;

	caps = info->amp_caps;

	mutex_unlock(&codec->hash_mutex);

	if (!cache_only)

int snd_hda_codec_amp_update(struct hda_codec *codec, hda_nid_t nid, int ch,

			     int direction, int idx, int mask, int val)

{

	return codec_amp_update(codec, nid, ch, direction, idx, mask, val, false);

	return codec_amp_update(codec, nid, ch, direction, idx, mask, val,

				false, codec->cached_write);

}

EXPORT_SYMBOL_GPL(snd_hda_codec_amp_update);

int snd_hda_codec_amp_init(struct hda_codec *codec, hda_nid_t nid, int ch,

			   int dir, int idx, int mask, int val)

{

	return codec_amp_update(codec, nid, ch, dir, idx, mask, val, true);

	return codec_amp_update(codec, nid, ch, dir, idx, mask, val, true,

				codec->cached_write);

}

EXPORT_SYMBOL_GPL(snd_hda_codec_amp_init);

	maxval = get_amp_max_value(codec, nid, dir, 0);

	if (val > maxval)

		val = maxval;

	return snd_hda_codec_amp_update(codec, nid, ch, dir, idx,

					HDA_AMP_VOLMASK, val);

	return codec_amp_update(codec, nid, ch, dir, idx, HDA_AMP_VOLMASK, val,

				false, !hda_codec_is_power_on(codec));

}

/**

	long *valp = ucontrol->value.integer.value;

	int change = 0;

	snd_hda_power_up(codec);

	if (chs & 1) {

		change = update_amp_value(codec, nid, 0, dir, idx, ofs, *valp);

		valp++;

	}

	if (chs & 2)

		change |= update_amp_value(codec, nid, 1, dir, idx, ofs, *valp);

	snd_hda_power_down(codec);

	return change;

}

EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_volume_put);

	long *valp = ucontrol->value.integer.value;

	int change = 0;

	snd_hda_power_up(codec);

	if (chs & 1) {

		change = snd_hda_codec_amp_update(codec, nid, 0, dir, idx,

		change = codec_amp_update(codec, nid, 0, dir, idx,

					  HDA_AMP_MUTE,

						  *valp ? 0 : HDA_AMP_MUTE);

					  *valp ? 0 : HDA_AMP_MUTE, false,

					  !hda_codec_is_power_on(codec));

		valp++;

	}

	if (chs & 2)

		change |= snd_hda_codec_amp_update(codec, nid, 1, dir, idx,

		change |= codec_amp_update(codec, nid, 1, dir, idx,

					   HDA_AMP_MUTE,

						   *valp ? 0 : HDA_AMP_MUTE);

					   *valp ? 0 : HDA_AMP_MUTE, false,

					   !hda_codec_is_power_on(codec));

	hda_call_check_power_status(codec, nid);

	snd_hda_power_down(codec);

	return change;

}

EXPORT_SYMBOL_GPL(snd_hda_mixer_amp_switch_put);

struct hda_codec;

struct hda_pcm;

struct hda_pcm_stream;

struct hda_bus_unsolicited;

/* NID type */

typedef u16 hda_nid_t;

#endif

};

/* template to pass to the bus constructor */

struct hda_bus_template {

	void *private_data;

	struct pci_dev *pci;

	const char *modelname;

	int *power_save;

	struct hda_bus_ops ops;

/* unsolicited event handler */

#define HDA_UNSOL_QUEUE_SIZE	64

struct hda_bus_unsolicited {

	/* ring buffer */

	u32 queue[HDA_UNSOL_QUEUE_SIZE * 2];

	unsigned int rp, wp;

	/* workqueue */

	struct work_struct work;

};

/*

struct hda_bus {

	struct snd_card *card;

	/* copied from template */

	void *private_data;

	struct pci_dev *pci;

	const char *modelname;

	struct mutex prepare_mutex;

	/* unsolicited event queue */

	struct hda_bus_unsolicited *unsol;

	struct hda_bus_unsolicited unsol;

	char workq_name[16];

	struct workqueue_struct *workq;	/* common workqueue for codecs */

/*

 * constructors

 */

int snd_hda_bus_new(struct snd_card *card, const struct hda_bus_template *temp,

		    struct hda_bus **busp);

int snd_hda_bus_new(struct snd_card *card, struct hda_bus **busp);

int snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr,

		      struct hda_codec **codecp);

int snd_hda_codec_configure(struct hda_codec *codec);

#include <linux/reboot.h>

#include <sound/core.h>

#include <sound/initval.h>

#include "hda_priv.h"

#include "hda_controller.h"

#define CREATE_TRACE_POINTS

	int i;

#ifdef CONFIG_PM

	if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)

	if (azx_has_pm_runtime(chip))

		if (!pm_runtime_active(chip->card->dev))

			return IRQ_NONE;

#endif

{

	struct azx *chip = bus->private_data;

	if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))

	if (!azx_has_pm_runtime(chip))

		return;

	if (power_up)

	return j;

}

/* Codec initialization */

int azx_codec_create(struct azx *chip, const char *model,

		     unsigned int max_slots,

		     int *power_save_to)

{

	struct hda_bus_template bus_temp;

	int c, codecs, err;

	memset(&bus_temp, 0, sizeof(bus_temp));

	bus_temp.private_data = chip;

	bus_temp.modelname = model;

	bus_temp.pci = chip->pci;

	bus_temp.ops.command = azx_send_cmd;

	bus_temp.ops.get_response = azx_get_response;

	bus_temp.ops.attach_pcm = azx_attach_pcm_stream;

	bus_temp.ops.bus_reset = azx_bus_reset;

static struct hda_bus_ops bus_ops = {

	.command = azx_send_cmd,

	.get_response = azx_get_response,

	.attach_pcm = azx_attach_pcm_stream,

	.bus_reset = azx_bus_reset,

#ifdef CONFIG_PM

	bus_temp.power_save = power_save_to;

	bus_temp.ops.pm_notify = azx_power_notify;

	.pm_notify = azx_power_notify,

#endif

#ifdef CONFIG_SND_HDA_DSP_LOADER

	bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;

	bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;

	bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;

	.load_dsp_prepare = azx_load_dsp_prepare,

	.load_dsp_trigger = azx_load_dsp_trigger,

	.load_dsp_cleanup = azx_load_dsp_cleanup,

#endif

};

	err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);

/* HD-audio bus initialization */

int azx_bus_create(struct azx *chip, const char *model, int *power_save_to)

{

	struct hda_bus *bus;

	int err;

	err = snd_hda_bus_new(chip->card, &bus);

	if (err < 0)

		return err;

	chip->bus = bus;

	bus->private_data = chip;

	bus->pci = chip->pci;

	bus->modelname = model;

	bus->ops = bus_ops;

#ifdef CONFIG_PM

	bus->power_save = power_save_to;

#endif

	if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {

		dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");

		chip->bus->needs_damn_long_delay = 1;

		bus->needs_damn_long_delay = 1;

	}

	/* AMD chipsets often cause the communication stalls upon certain

	 * sequence like the pin-detection.  It seems that forcing the synced

	 * access works around the stall.  Grrr...

	 */

	if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {

		dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");

		bus->sync_write = 1;

		bus->allow_bus_reset = 1;

	}

	return 0;

}

EXPORT_SYMBOL_GPL(azx_bus_create);

/* Probe codecs */

int azx_probe_codecs(struct azx *chip, unsigned int max_slots)

{

	struct hda_bus *bus = chip->bus;

	int c, codecs, err;

	codecs = 0;

	if (!max_slots)

		max_slots = AZX_DEFAULT_CODECS;

		}

	}

	/* AMD chipsets often cause the communication stalls upon certain

	 * sequence like the pin-detection.  It seems that forcing the synced

	 * access works around the stall.  Grrr...

	 */

	if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {

		dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");

		chip->bus->sync_write = 1;

		chip->bus->allow_bus_reset = 1;

	}

	/* Then create codec instances */

	for (c = 0; c < max_slots; c++) {

		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {

			struct hda_codec *codec;

			err = snd_hda_codec_new(chip->bus, c, &codec);

			err = snd_hda_codec_new(bus, c, &codec);

			if (err < 0)

				continue;

			codec->jackpoll_interval = get_jackpoll_interval(chip);

	}

	return 0;

}

EXPORT_SYMBOL_GPL(azx_codec_create);

EXPORT_SYMBOL_GPL(azx_probe_codecs);

/* configure each codec instance */

int azx_codec_configure(struct azx *chip)

}

EXPORT_SYMBOL_GPL(azx_codec_configure);

/* mixer creation - all stuff is implemented in hda module */

int azx_mixer_create(struct azx *chip)

{

	return snd_hda_build_controls(chip->bus);

}

EXPORT_SYMBOL_GPL(azx_mixer_create);

static bool is_input_stream(struct azx *chip, unsigned char index)

{

#ifndef __SOUND_HDA_CONTROLLER_H

#define __SOUND_HDA_CONTROLLER_H

#include <linux/timecounter.h>

#include <linux/interrupt.h>

#include <sound/core.h>

#include <sound/pcm.h>

#include <sound/initval.h>

#include "hda_codec.h"

#include "hda_priv.h"

/*

 * registers

 */

#define AZX_REG_GCAP			0x00

#define   AZX_GCAP_64OK		(1 << 0)   /* 64bit address support */

#define   AZX_GCAP_NSDO		(3 << 1)   /* # of serial data out signals */

#define   AZX_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */

#define   AZX_GCAP_ISS		(15 << 8)  /* # of input streams */

#define   AZX_GCAP_OSS		(15 << 12) /* # of output streams */

#define AZX_REG_VMIN			0x02

#define AZX_REG_VMAJ			0x03

#define AZX_REG_OUTPAY			0x04

#define AZX_REG_INPAY			0x06

#define AZX_REG_GCTL			0x08

#define   AZX_GCTL_RESET	(1 << 0)   /* controller reset */

#define   AZX_GCTL_FCNTRL	(1 << 1)   /* flush control */

#define   AZX_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */

#define AZX_REG_WAKEEN			0x0c

#define AZX_REG_STATESTS		0x0e

#define AZX_REG_GSTS			0x10

#define   AZX_GSTS_FSTS		(1 << 1)   /* flush status */

#define AZX_REG_INTCTL			0x20

#define AZX_REG_INTSTS			0x24

#define AZX_REG_WALLCLK			0x30	/* 24Mhz source */

#define AZX_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */

#define AZX_REG_SSYNC			0x38

#define AZX_REG_CORBLBASE		0x40

#define AZX_REG_CORBUBASE		0x44

#define AZX_REG_CORBWP			0x48

#define AZX_REG_CORBRP			0x4a

#define   AZX_CORBRP_RST	(1 << 15)  /* read pointer reset */

#define AZX_REG_CORBCTL			0x4c

#define   AZX_CORBCTL_RUN	(1 << 1)   /* enable DMA */

#define   AZX_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */

#define AZX_REG_CORBSTS			0x4d

#define   AZX_CORBSTS_CMEI	(1 << 0)   /* memory error indication */

#define AZX_REG_CORBSIZE		0x4e

#define AZX_REG_RIRBLBASE		0x50

#define AZX_REG_RIRBUBASE		0x54

#define AZX_REG_RIRBWP			0x58

#define   AZX_RIRBWP_RST	(1 << 15)  /* write pointer reset */

#define AZX_REG_RINTCNT			0x5a

#define AZX_REG_RIRBCTL			0x5c

#define   AZX_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */

#define   AZX_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */

#define   AZX_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */

#define AZX_REG_RIRBSTS			0x5d

#define   AZX_RBSTS_IRQ		(1 << 0)   /* response irq */

#define   AZX_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */

#define AZX_REG_RIRBSIZE		0x5e

#define AZX_REG_IC			0x60

#define AZX_REG_IR			0x64

#define AZX_REG_IRS			0x68

#define   AZX_IRS_VALID		(1<<1)

#define   AZX_IRS_BUSY		(1<<0)

#define AZX_REG_DPLBASE			0x70

#define AZX_REG_DPUBASE			0x74

#define   AZX_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */

enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */

#define AZX_REG_SD_CTL			0x00

#define AZX_REG_SD_STS			0x03

#define AZX_REG_SD_LPIB			0x04

#define AZX_REG_SD_CBL			0x08

#define AZX_REG_SD_LVI			0x0c

#define AZX_REG_SD_FIFOW		0x0e

#define AZX_REG_SD_FIFOSIZE		0x10

#define AZX_REG_SD_FORMAT		0x12

#define AZX_REG_SD_BDLPL		0x18

#define AZX_REG_SD_BDLPU		0x1c

/* PCI space */

#define AZX_PCIREG_TCSEL		0x44

/*

 * other constants

 */

/* max number of fragments - we may use more if allocating more pages for BDL */

#define BDL_SIZE		4096

#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)

#define AZX_MAX_FRAG		32

/* max buffer size - no h/w limit, you can increase as you like */

#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */

#define RIRB_INT_RESPONSE	0x01

#define RIRB_INT_OVERRUN	0x04

#define RIRB_INT_MASK		0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */

#define AZX_MAX_CODECS		8

#define AZX_DEFAULT_CODECS	4

#define STATESTS_INT_MASK	((1 << AZX_MAX_CODECS) - 1)

/* SD_CTL bits */

#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */

#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */

#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */

#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */

#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */

#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)

#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */

#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */

#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */

#define SD_INT_COMPLETE		0x04	/* completion interrupt */

#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\

				 SD_INT_COMPLETE)

/* SD_STS */

#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */

#define AZX_INT_ALL_STREAM	0xff	   /* all stream interrupts */

#define AZX_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */

#define AZX_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */

#define AZX_MAX_CORB_ENTRIES	256

#define AZX_MAX_RIRB_ENTRIES	256

/* driver quirks (capabilities) */

/* bits 0-7 are used for indicating driver type */

#define AZX_DCAPS_NO_TCSEL	(1 << 8)	/* No Intel TCSEL bit */

#define AZX_DCAPS_NO_MSI	(1 << 9)	/* No MSI support */

#define AZX_DCAPS_SNOOP_MASK	(3 << 10)	/* snoop type mask */

#define AZX_DCAPS_SNOOP_OFF	(1 << 12)	/* snoop default off */

#define AZX_DCAPS_RIRB_DELAY	(1 << 13)	/* Long delay in read loop */

#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)	/* Put a delay before read */

#define AZX_DCAPS_CTX_WORKAROUND (1 << 15)	/* X-Fi workaround */

#define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */

#define AZX_DCAPS_POSFIX_VIA	(1 << 17)	/* Use VIACOMBO as default */

#define AZX_DCAPS_NO_64BIT	(1 << 18)	/* No 64bit address */

#define AZX_DCAPS_SYNC_WRITE	(1 << 19)	/* sync each cmd write */

#define AZX_DCAPS_OLD_SSYNC	(1 << 20)	/* Old SSYNC reg for ICH */

#define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21)	/* no buffer size alignment */

/* 22 unused */

#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)	/* BDLE in 4k boundary */

#define AZX_DCAPS_REVERSE_ASSIGN (1 << 24)	/* Assign devices in reverse order */

#define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */

#define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */

#define AZX_DCAPS_I915_POWERWELL (1 << 27)	/* HSW i915 powerwell support */

#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)	/* CORBRP clears itself after reset */

#define AZX_DCAPS_NO_MSI64      (1 << 29)	/* Stick to 32-bit MSIs */

#define AZX_DCAPS_SEPARATE_STREAM_TAG	(1 << 30) /* capture and playback use separate stream tag */

enum {

	AZX_SNOOP_TYPE_NONE,

	AZX_SNOOP_TYPE_SCH,

	AZX_SNOOP_TYPE_ATI,

	AZX_SNOOP_TYPE_NVIDIA,

};

/* HD Audio class code */

#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403

struct azx_dev {

	struct snd_dma_buffer bdl; /* BDL buffer */

	u32 *posbuf;		/* position buffer pointer */

	unsigned int bufsize;	/* size of the play buffer in bytes */

	unsigned int period_bytes; /* size of the period in bytes */

	unsigned int frags;	/* number for period in the play buffer */

	unsigned int fifo_size;	/* FIFO size */

	unsigned long start_wallclk;	/* start + minimum wallclk */

	unsigned long period_wallclk;	/* wallclk for period */

	void __iomem *sd_addr;	/* stream descriptor pointer */

	u32 sd_int_sta_mask;	/* stream int status mask */

	/* pcm support */

	struct snd_pcm_substream *substream;	/* assigned substream,

						 * set in PCM open

						 */

	unsigned int format_val;	/* format value to be set in the

					 * controller and the codec

					 */

	unsigned char stream_tag;	/* assigned stream */

	unsigned char index;		/* stream index */

	int assigned_key;		/* last device# key assigned to */

	unsigned int opened:1;

	unsigned int running:1;

	unsigned int irq_pending:1;

	unsigned int prepared:1;

	unsigned int locked:1;

	/*

	 * For VIA:

	 *  A flag to ensure DMA position is 0

	 *  when link position is not greater than FIFO size

	 */

	unsigned int insufficient:1;

	unsigned int wc_marked:1;

	unsigned int no_period_wakeup:1;

	struct timecounter  azx_tc;

	struct cyclecounter azx_cc;

	int delay_negative_threshold;

#ifdef CONFIG_SND_HDA_DSP_LOADER

	/* Allows dsp load to have sole access to the playback stream. */

	struct mutex dsp_mutex;

#endif

};

/* CORB/RIRB */

struct azx_rb {

	u32 *buf;		/* CORB/RIRB buffer

				 * Each CORB entry is 4byte, RIRB is 8byte

				 */

	dma_addr_t addr;	/* physical address of CORB/RIRB buffer */

	/* for RIRB */

	unsigned short rp, wp;	/* read/write pointers */

	int cmds[AZX_MAX_CODECS];	/* number of pending requests */

	u32 res[AZX_MAX_CODECS];	/* last read value */

};

struct azx;

/* Functions to read/write to hda registers. */

struct hda_controller_ops {

	/* Register Access */

	void (*reg_writel)(u32 value, u32 __iomem *addr);

	u32 (*reg_readl)(u32 __iomem *addr);

	void (*reg_writew)(u16 value, u16 __iomem *addr);

	u16 (*reg_readw)(u16 __iomem *addr);

	void (*reg_writeb)(u8 value, u8 __iomem *addr);

	u8 (*reg_readb)(u8 __iomem *addr);

	/* Disable msi if supported, PCI only */

	int (*disable_msi_reset_irq)(struct azx *);

	/* Allocation ops */

	int (*dma_alloc_pages)(struct azx *chip,