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Commit 8cd37370 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next 

- a fix from Eric for synchronization with etnaviv exported dma-bufs
- thermal throttle support for newer GPU cores
- updated module clock gating to work around GPU errata
- a fix to restore userspace buffer cache performance

* 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux:
  drm/etnaviv: restore ETNA_PREP_NOSYNC behaviour
  drm/etnaviv: implement cooling support for new GPU cores
  drm/etnaviv: update MLCG disables with info from newer Vivante driver
  drm/etnaviv: update common.xml.h
  drm/etnaviv: Expose our reservation object when exporting a dmabuf.
parents 6d61e70c 46a269da

drivers/gpu/drm/etnaviv/common.xml.h

+89 −61
Original line number Original line Diff line number Diff line
@@ -8,10 +8,38 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone git://0x04.net/rules-ng-ng

git clone git://0x04.net/rules-ng-ng





The rules-ng-ng source files this header was generated from are:

The rules-ng-ng source files this header was generated from are:

- state_hi.xml (  24309 bytes, from 2015-12-12 09:02:53)

- state.xml     (  19930 bytes, from 2017-03-09 15:43:43)

- common.xml   (  18379 bytes, from 2015-12-12 09:02:53)

- common.xml    (  23473 bytes, from 2017-03-09 15:43:43)

- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)

- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)

- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)

- state_3d.xml  (  66957 bytes, from 2017-03-09 15:43:43)

- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)





Copyright (C) 2015

Copyright (C) 2012-2017 by the following authors:

- Wladimir J. van der Laan <laanwj@gmail.com>

- Christian Gmeiner <christian.gmeiner@gmail.com>

- Lucas Stach <l.stach@pengutronix.de>

- Russell King <rmk@arm.linux.org.uk>



Permission is hereby granted, free of charge, to any person obtaining a

copy of this software and associated documentation files (the "Software"),

to deal in the Software without restriction, including without limitation

the rights to use, copy, modify, merge, publish, distribute, sub license,

and/or sell copies of the Software, and to permit persons to whom the

Software is furnished to do so, subject to the following conditions:



The above copyright notice and this permission notice (including the

next paragraph) shall be included in all copies or substantial portions

of the Software.



THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL

THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

DEALINGS IN THE SOFTWARE.

*/

*/
@@ -162,129 +190,129 @@ Copyright (C) 2015 
#define chipMinorFeatures1_FC_FLUSH_STALL			0x80000000

#define chipMinorFeatures1_FC_FLUSH_STALL			0x80000000

#define chipMinorFeatures2_LINE_LOOP				0x00000001

#define chipMinorFeatures2_LINE_LOOP				0x00000001

#define chipMinorFeatures2_LOGIC_OP				0x00000002

#define chipMinorFeatures2_LOGIC_OP				0x00000002

#define chipMinorFeatures2_UNK2					0x00000004

#define chipMinorFeatures2_SEAMLESS_CUBE_MAP			0x00000004

#define chipMinorFeatures2_SUPERTILED_TEXTURE			0x00000008

#define chipMinorFeatures2_SUPERTILED_TEXTURE			0x00000008

#define chipMinorFeatures2_UNK4					0x00000010

#define chipMinorFeatures2_LINEAR_PE				0x00000010

#define chipMinorFeatures2_RECT_PRIMITIVE			0x00000020

#define chipMinorFeatures2_RECT_PRIMITIVE			0x00000020

#define chipMinorFeatures2_COMPOSITION				0x00000040

#define chipMinorFeatures2_COMPOSITION				0x00000040

#define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT		0x00000080

#define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT		0x00000080

#define chipMinorFeatures2_UNK8					0x00000100

#define chipMinorFeatures2_PE_SWIZZLE				0x00000100

#define chipMinorFeatures2_UNK9					0x00000200

#define chipMinorFeatures2_END_EVENT				0x00000200

#define chipMinorFeatures2_UNK10				0x00000400

#define chipMinorFeatures2_S1S8					0x00000400

#define chipMinorFeatures2_HALTI1				0x00000800

#define chipMinorFeatures2_HALTI1				0x00000800

#define chipMinorFeatures2_UNK12				0x00001000

#define chipMinorFeatures2_RGB888				0x00001000

#define chipMinorFeatures2_UNK13				0x00002000

#define chipMinorFeatures2_TX__YUV_ASSEMBLER			0x00002000

#define chipMinorFeatures2_UNK14				0x00004000

#define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING		0x00004000

#define chipMinorFeatures2_EXTRA_TEXTURE_STATE			0x00008000

#define chipMinorFeatures2_EXTRA_TEXTURE_STATE			0x00008000

#define chipMinorFeatures2_FULL_DIRECTFB			0x00010000

#define chipMinorFeatures2_FULL_DIRECTFB			0x00010000

#define chipMinorFeatures2_2D_TILING				0x00020000

#define chipMinorFeatures2_2D_TILING				0x00020000

#define chipMinorFeatures2_THREAD_WALKER_IN_PS			0x00040000

#define chipMinorFeatures2_THREAD_WALKER_IN_PS			0x00040000

#define chipMinorFeatures2_TILE_FILLER				0x00080000

#define chipMinorFeatures2_TILE_FILLER				0x00080000

#define chipMinorFeatures2_UNK20				0x00100000

#define chipMinorFeatures2_YUV_STANDARD				0x00100000

#define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT			0x00200000

#define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT			0x00200000

#define chipMinorFeatures2_UNK22				0x00400000

#define chipMinorFeatures2_YUV_CONVERSION			0x00400000

#define chipMinorFeatures2_UNK23				0x00800000

#define chipMinorFeatures2_FLUSH_FIXED_2D			0x00800000

#define chipMinorFeatures2_UNK24				0x01000000

#define chipMinorFeatures2_INTERLEAVER				0x01000000

#define chipMinorFeatures2_MIXED_STREAMS			0x02000000

#define chipMinorFeatures2_MIXED_STREAMS			0x02000000

#define chipMinorFeatures2_2D_420_L2CACHE			0x04000000

#define chipMinorFeatures2_2D_420_L2CACHE			0x04000000

#define chipMinorFeatures2_UNK27				0x08000000

#define chipMinorFeatures2_BUG_FIXES7				0x08000000

#define chipMinorFeatures2_2D_NO_INDEX8_BRUSH			0x10000000

#define chipMinorFeatures2_2D_NO_INDEX8_BRUSH			0x10000000

#define chipMinorFeatures2_TEXTURE_TILED_READ			0x20000000

#define chipMinorFeatures2_TEXTURE_TILED_READ			0x20000000

#define chipMinorFeatures2_UNK30				0x40000000

#define chipMinorFeatures2_DECOMPRESS_Z16			0x40000000

#define chipMinorFeatures2_UNK31				0x80000000

#define chipMinorFeatures2_BUG_FIXES8				0x80000000

#define chipMinorFeatures3_ROTATION_STALL_FIX			0x00000001

#define chipMinorFeatures3_ROTATION_STALL_FIX			0x00000001

#define chipMinorFeatures3_UNK1					0x00000002

#define chipMinorFeatures3_OCL_ONLY				0x00000002

#define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX		0x00000004

#define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX		0x00000004

#define chipMinorFeatures3_UNK3					0x00000008

#define chipMinorFeatures3_INSTRUCTION_CACHE			0x00000008

#define chipMinorFeatures3_UNK4					0x00000010

#define chipMinorFeatures3_GEOMETRY_SHADER			0x00000010

#define chipMinorFeatures3_UNK5					0x00000020

#define chipMinorFeatures3_TEX_COMPRESSION_SUPERTILED		0x00000020

#define chipMinorFeatures3_UNK6					0x00000040

#define chipMinorFeatures3_GENERICS				0x00000040

#define chipMinorFeatures3_UNK7					0x00000080

#define chipMinorFeatures3_BUG_FIXES9				0x00000080

#define chipMinorFeatures3_FAST_MSAA				0x00000100

#define chipMinorFeatures3_FAST_MSAA				0x00000100

#define chipMinorFeatures3_UNK9					0x00000200

#define chipMinorFeatures3_WCLIP				0x00000200

#define chipMinorFeatures3_BUG_FIXES10				0x00000400

#define chipMinorFeatures3_BUG_FIXES10				0x00000400

#define chipMinorFeatures3_UNK11				0x00000800

#define chipMinorFeatures3_UNIFIED_SAMPLERS			0x00000800

#define chipMinorFeatures3_BUG_FIXES11				0x00001000

#define chipMinorFeatures3_BUG_FIXES11				0x00001000

#define chipMinorFeatures3_UNK13				0x00002000

#define chipMinorFeatures3_PERFORMANCE_COUNTERS			0x00002000

#define chipMinorFeatures3_UNK14				0x00004000

#define chipMinorFeatures3_HAS_FAST_TRANSCENDENTALS		0x00004000

#define chipMinorFeatures3_UNK15				0x00008000

#define chipMinorFeatures3_BUG_FIXES12				0x00008000

#define chipMinorFeatures3_UNK16				0x00010000

#define chipMinorFeatures3_BUG_FIXES13				0x00010000

#define chipMinorFeatures3_UNK17				0x00020000

#define chipMinorFeatures3_DE_ENHANCEMENTS1			0x00020000

#define chipMinorFeatures3_ACE					0x00040000

#define chipMinorFeatures3_ACE					0x00040000

#define chipMinorFeatures3_UNK19				0x00080000

#define chipMinorFeatures3_TX_ENHANCEMENTS1			0x00080000

#define chipMinorFeatures3_UNK20				0x00100000

#define chipMinorFeatures3_SH_ENHANCEMENTS1			0x00100000

#define chipMinorFeatures3_UNK21				0x00200000

#define chipMinorFeatures3_SH_ENHANCEMENTS2			0x00200000

#define chipMinorFeatures3_UNK22				0x00400000

#define chipMinorFeatures3_UNK22				0x00400000

#define chipMinorFeatures3_UNK23				0x00800000

#define chipMinorFeatures3_2D_FC_SOURCE				0x00800000

#define chipMinorFeatures3_UNK24				0x01000000

#define chipMinorFeatures3_UNK24				0x01000000

#define chipMinorFeatures3_UNK25				0x02000000

#define chipMinorFeatures3_UNK25				0x02000000

#define chipMinorFeatures3_NEW_HZ				0x04000000

#define chipMinorFeatures3_NEW_HZ				0x04000000

#define chipMinorFeatures3_UNK27				0x08000000

#define chipMinorFeatures3_UNK27				0x08000000

#define chipMinorFeatures3_UNK28				0x10000000

#define chipMinorFeatures3_UNK28				0x10000000

#define chipMinorFeatures3_UNK29				0x20000000

#define chipMinorFeatures3_SH_ENHANCEMENTS3			0x20000000

#define chipMinorFeatures3_UNK30				0x40000000

#define chipMinorFeatures3_UNK30				0x40000000

#define chipMinorFeatures3_UNK31				0x80000000

#define chipMinorFeatures3_UNK31				0x80000000

#define chipMinorFeatures4_UNK0					0x00000001

#define chipMinorFeatures4_UNK0					0x00000001

#define chipMinorFeatures4_UNK1					0x00000002

#define chipMinorFeatures4_PE_ENHANCEMENTS2			0x00000002

#define chipMinorFeatures4_UNK2					0x00000004

#define chipMinorFeatures4_FRUSTUM_CLIP_FIX			0x00000004

#define chipMinorFeatures4_UNK3					0x00000008

#define chipMinorFeatures4_UNK3					0x00000008

#define chipMinorFeatures4_UNK4					0x00000010

#define chipMinorFeatures4_UNK4					0x00000010

#define chipMinorFeatures4_UNK5					0x00000020

#define chipMinorFeatures4_2D_GAMMA				0x00000020

#define chipMinorFeatures4_UNK6					0x00000040

#define chipMinorFeatures4_SINGLE_BUFFER			0x00000040

#define chipMinorFeatures4_UNK7					0x00000080

#define chipMinorFeatures4_UNK7					0x00000080

#define chipMinorFeatures4_UNK8					0x00000100

#define chipMinorFeatures4_UNK8					0x00000100

#define chipMinorFeatures4_UNK9					0x00000200

#define chipMinorFeatures4_UNK9					0x00000200

#define chipMinorFeatures4_UNK10				0x00000400

#define chipMinorFeatures4_UNK10				0x00000400

#define chipMinorFeatures4_UNK11				0x00000800

#define chipMinorFeatures4_TX_LERP_PRECISION_FIX		0x00000800

#define chipMinorFeatures4_UNK12				0x00001000

#define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION		0x00001000

#define chipMinorFeatures4_UNK13				0x00002000

#define chipMinorFeatures4_TEXTURE_ASTC				0x00002000

#define chipMinorFeatures4_UNK14				0x00004000

#define chipMinorFeatures4_UNK14				0x00004000

#define chipMinorFeatures4_UNK15				0x00008000

#define chipMinorFeatures4_UNK15				0x00008000

#define chipMinorFeatures4_HALTI2				0x00010000

#define chipMinorFeatures4_HALTI2				0x00010000

#define chipMinorFeatures4_UNK17				0x00020000

#define chipMinorFeatures4_UNK17				0x00020000

#define chipMinorFeatures4_SMALL_MSAA				0x00040000

#define chipMinorFeatures4_SMALL_MSAA				0x00040000

#define chipMinorFeatures4_UNK19				0x00080000

#define chipMinorFeatures4_UNK19				0x00080000

#define chipMinorFeatures4_UNK20				0x00100000

#define chipMinorFeatures4_NEW_RA				0x00100000

#define chipMinorFeatures4_UNK21				0x00200000

#define chipMinorFeatures4_2D_OPF_YUV_OUTPUT			0x00200000

#define chipMinorFeatures4_UNK22				0x00400000

#define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2		0x00400000

#define chipMinorFeatures4_UNK23				0x00800000

#define chipMinorFeatures4_NO_USER_CSC				0x00800000

#define chipMinorFeatures4_UNK24				0x01000000

#define chipMinorFeatures4_ZFIXES				0x01000000

#define chipMinorFeatures4_UNK25				0x02000000

#define chipMinorFeatures4_BUG_FIXES18				0x02000000

#define chipMinorFeatures4_UNK26				0x04000000

#define chipMinorFeatures4_2D_COMPRESSION			0x04000000

#define chipMinorFeatures4_UNK27				0x08000000

#define chipMinorFeatures4_PROBE				0x08000000

#define chipMinorFeatures4_UNK28				0x10000000

#define chipMinorFeatures4_UNK28				0x10000000

#define chipMinorFeatures4_UNK29				0x20000000

#define chipMinorFeatures4_2D_SUPER_TILE_VERSION		0x20000000

#define chipMinorFeatures4_UNK30				0x40000000

#define chipMinorFeatures4_UNK30				0x40000000

#define chipMinorFeatures4_UNK31				0x80000000

#define chipMinorFeatures4_UNK31				0x80000000

#define chipMinorFeatures5_UNK0					0x00000001

#define chipMinorFeatures5_UNK0					0x00000001

#define chipMinorFeatures5_UNK1					0x00000002

#define chipMinorFeatures5_UNK1					0x00000002

#define chipMinorFeatures5_UNK2					0x00000004

#define chipMinorFeatures5_UNK2					0x00000004

#define chipMinorFeatures5_UNK3					0x00000008

#define chipMinorFeatures5_UNK3					0x00000008

#define chipMinorFeatures5_UNK4					0x00000010

#define chipMinorFeatures5_EEZ					0x00000010

#define chipMinorFeatures5_UNK5					0x00000020

#define chipMinorFeatures5_UNK5					0x00000020

#define chipMinorFeatures5_UNK6					0x00000040

#define chipMinorFeatures5_UNK6					0x00000040

#define chipMinorFeatures5_UNK7					0x00000080

#define chipMinorFeatures5_UNK7					0x00000080

#define chipMinorFeatures5_UNK8					0x00000100

#define chipMinorFeatures5_UNK8					0x00000100

#define chipMinorFeatures5_HALTI3				0x00000200

#define chipMinorFeatures5_HALTI3				0x00000200

#define chipMinorFeatures5_UNK10				0x00000400

#define chipMinorFeatures5_UNK10				0x00000400

#define chipMinorFeatures5_UNK11				0x00000800

#define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP		0x00000800

#define chipMinorFeatures5_UNK12				0x00001000

#define chipMinorFeatures5_UNK12				0x00001000

#define chipMinorFeatures5_UNK13				0x00002000

#define chipMinorFeatures5_SEPARATE_SRC_DST			0x00002000

#define chipMinorFeatures5_UNK14				0x00004000

#define chipMinorFeatures5_HALTI4				0x00004000

#define chipMinorFeatures5_UNK15				0x00008000

#define chipMinorFeatures5_UNK15				0x00008000

#define chipMinorFeatures5_UNK16				0x00010000

#define chipMinorFeatures5_ANDROID_ONLY				0x00010000

#define chipMinorFeatures5_UNK17				0x00020000

#define chipMinorFeatures5_HAS_PRODUCTID			0x00020000

#define chipMinorFeatures5_UNK18				0x00040000

#define chipMinorFeatures5_UNK18				0x00040000

#define chipMinorFeatures5_UNK19				0x00080000

#define chipMinorFeatures5_UNK19				0x00080000

#define chipMinorFeatures5_UNK20				0x00100000

#define chipMinorFeatures5_PE_DITHER_FIX2			0x00100000

#define chipMinorFeatures5_UNK21				0x00200000

#define chipMinorFeatures5_UNK21				0x00200000

#define chipMinorFeatures5_UNK22				0x00400000

#define chipMinorFeatures5_UNK22				0x00400000

#define chipMinorFeatures5_UNK23				0x00800000

#define chipMinorFeatures5_UNK23				0x00800000

#define chipMinorFeatures5_UNK24				0x01000000

#define chipMinorFeatures5_UNK24				0x01000000

#define chipMinorFeatures5_UNK25				0x02000000

#define chipMinorFeatures5_UNK25				0x02000000

#define chipMinorFeatures5_UNK26				0x04000000

#define chipMinorFeatures5_UNK26				0x04000000

#define chipMinorFeatures5_UNK27				0x08000000

#define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT	0x08000000

#define chipMinorFeatures5_UNK28				0x10000000

#define chipMinorFeatures5_V2_MSAA_COMP_FIX			0x10000000

#define chipMinorFeatures5_UNK29				0x20000000

#define chipMinorFeatures5_UNK29				0x20000000

#define chipMinorFeatures5_UNK30				0x40000000

#define chipMinorFeatures5_UNK30				0x40000000

#define chipMinorFeatures5_UNK31				0x80000000

#define chipMinorFeatures5_UNK31				0x80000000

drivers/gpu/drm/etnaviv/etnaviv_drv.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -495,6 +495,7 @@ static struct drm_driver etnaviv_drm_driver = { 
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,

	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,

	.gem_prime_export   = drm_gem_prime_export,

	.gem_prime_export   = drm_gem_prime_export,

	.gem_prime_import   = drm_gem_prime_import,

	.gem_prime_import   = drm_gem_prime_import,

	.gem_prime_res_obj  = etnaviv_gem_prime_res_obj,

	.gem_prime_pin      = etnaviv_gem_prime_pin,

	.gem_prime_pin      = etnaviv_gem_prime_pin,

	.gem_prime_unpin    = etnaviv_gem_prime_unpin,

	.gem_prime_unpin    = etnaviv_gem_prime_unpin,

	.gem_prime_get_sg_table = etnaviv_gem_prime_get_sg_table,

	.gem_prime_get_sg_table = etnaviv_gem_prime_get_sg_table,

drivers/gpu/drm/etnaviv/etnaviv_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -80,6 +80,7 @@ void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj); 
void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);

void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);

int etnaviv_gem_prime_mmap(struct drm_gem_object *obj,

int etnaviv_gem_prime_mmap(struct drm_gem_object *obj,

			   struct vm_area_struct *vma);

			   struct vm_area_struct *vma);

struct reservation_object *etnaviv_gem_prime_res_obj(struct drm_gem_object *obj);

struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev,

struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev,

	struct dma_buf_attachment *attach, struct sg_table *sg);

	struct dma_buf_attachment *attach, struct sg_table *sg);

int etnaviv_gem_prime_pin(struct drm_gem_object *obj);

int etnaviv_gem_prime_pin(struct drm_gem_object *obj);

drivers/gpu/drm/etnaviv/etnaviv_gem.c

+14 −10
Original line number Original line Diff line number Diff line
@@ -411,16 +411,20 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, 
	struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);

	struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);

	struct drm_device *dev = obj->dev;

	struct drm_device *dev = obj->dev;

	bool write = !!(op & ETNA_PREP_WRITE);

	bool write = !!(op & ETNA_PREP_WRITE);

	unsigned long remain =

	int ret;

		op & ETNA_PREP_NOSYNC ? 0 : etnaviv_timeout_to_jiffies(timeout);



	long lret;

	if (op & ETNA_PREP_NOSYNC) {

		if (!reservation_object_test_signaled_rcu(etnaviv_obj->resv,

							  write))

			return -EBUSY;

	} else {

		unsigned long remain = etnaviv_timeout_to_jiffies(timeout);





	lret = reservation_object_wait_timeout_rcu(etnaviv_obj->resv,

		ret = reservation_object_wait_timeout_rcu(etnaviv_obj->resv,

							  write, true, remain);

							  write, true, remain);

	if (lret < 0)

		if (ret <= 0)

		return lret;

			return ret == 0 ? -ETIMEDOUT : ret;

	else if (lret == 0)

	}

		return remain == 0 ? -EBUSY : -ETIMEDOUT;





	if (etnaviv_obj->flags & ETNA_BO_CACHED) {

	if (etnaviv_obj->flags & ETNA_BO_CACHED) {

		if (!etnaviv_obj->sgt) {

		if (!etnaviv_obj->sgt) {

drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -150,3 +150,10 @@ struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev, 




	return ERR_PTR(ret);

	return ERR_PTR(ret);

}

}



struct reservation_object *etnaviv_gem_prime_res_obj(struct drm_gem_object *obj)

{

	struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);



	return etnaviv_obj->resv;

}