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Commit 8a1deb32 authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
Browse files

drm/i915/glk: Add cold boot sequence for GLK DSI 



As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. If cold boot
scenario detected in enable IO, then prepare port immediately.
In normal boot scenario, prepare port after glk_dsi_device_ready().
Without cold boot sequence enabled, features like S3/S4 doesn't work.

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497340095-5877-2-git-send-email-madhav.chauhan@intel.com
parent 74e4ce6a

drivers/gpu/drm/i915/intel_dsi.c

+51 −28
Original line number Diff line number Diff line
@@ -346,12 +346,13 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, 
	return true;

}



static void glk_dsi_enable_io(struct intel_encoder *encoder)

static bool glk_dsi_enable_io(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	enum port port;

	u32 tmp;

	bool cold_boot = false;



	/* Set the MIPI mode

	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
@@ -370,6 +371,9 @@ static void glk_dsi_enable_io(struct intel_encoder *encoder) 
	/* Program LP Wake */

	for_each_dsi_port(port, intel_dsi->ports) {

		tmp = I915_READ(MIPI_CTRL(port));

		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))

			tmp &= ~GLK_LP_WAKE;

		else

			tmp |= GLK_LP_WAKE;

		I915_WRITE(MIPI_CTRL(port), tmp);

	}
@@ -381,6 +385,14 @@ static void glk_dsi_enable_io(struct intel_encoder *encoder) 
				GLK_MIPIIO_PORT_POWERED, 20))

			DRM_ERROR("MIPIO port is powergated\n");

	}



	/* Check for cold boot scenario */

	for_each_dsi_port(port, intel_dsi->ports) {

		cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &

							DEVICE_READY);

	}



	return cold_boot;

}



static void glk_dsi_device_ready(struct intel_encoder *encoder)
@@ -410,8 +422,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) 
			val |= DEVICE_READY;

			I915_WRITE(MIPI_DEVICE_READY(port), val);

			usleep_range(10, 15);

		}



		} else {

			/* Enter ULPS */

			val = I915_READ(MIPI_DEVICE_READY(port));

			val &= ~ULPS_STATE_MASK;
@@ -439,6 +450,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) 
			val &= ~GLK_LP_WAKE;

			I915_WRITE(MIPI_CTRL(port), val);

		}

	}



	/* Wait for Stop state */

	for_each_dsi_port(port, intel_dsi->ports) {
@@ -778,6 +790,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, 
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	enum port port;

	u32 val;

	bool glk_cold_boot = false;



	DRM_DEBUG_KMS("\n");
@@ -808,6 +821,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, 
		I915_WRITE(DSPCLK_GATE_D, val);

	}



	if (!IS_GEMINILAKE(dev_priv))

		intel_dsi_prepare(encoder, pipe_config);



	/* Power on, try both CRC pmic gpio and VBT */
@@ -819,12 +833,21 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, 
	/* Deassert reset */

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);



	if (IS_GEMINILAKE(dev_priv))

		glk_dsi_enable_io(encoder);

	if (IS_GEMINILAKE(dev_priv)) {

		glk_cold_boot = glk_dsi_enable_io(encoder);



		/* Prepare port in cold boot(s3/s4) scenario */

		if (glk_cold_boot)

			intel_dsi_prepare(encoder, pipe_config);

	}



	/* Put device in ready state (LP-11) */

	intel_dsi_device_ready(encoder);



	/* Prepare port in normal boot scenario */

	if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)

		intel_dsi_prepare(encoder, pipe_config);



	/* Send initialization commands in LP mode */

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);