Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 898822ce authored by Zhao Yakui's avatar Zhao Yakui Committed by Eric Anholt
Browse files

drm/i915: Enable/disable the dithering for LVDS based on VBT setting 



Enable/disable the dithering for LVDS based on VBT setting. On the 965/g4x
platform the dithering flag is defined in LVDS register. And on the ironlake
the dithering flag is defined in pipeconf register.

Signed-off-by: default avatarZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent e3d8affb

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -975,6 +975,8 @@ 
#define   LVDS_PORT_EN			(1 << 31)

/* Selects pipe B for LVDS data.  Must be set on pre-965. */

#define   LVDS_PIPEB_SELECT		(1 << 30)

/* LVDS dithering flag on 965/g4x platform */

#define   LVDS_ENABLE_DITHER		(1 << 25)

/* Enable border for unscaled (or aspect-scaled) display */

#define   LVDS_BORDER_ENABLE		(1 << 15)

/*
@@ -1744,6 +1746,8 @@ 


/* Display & cursor control */



/* dithering flag on Ironlake */

#define PIPE_ENABLE_DITHER	(1 << 4)

/* Pipe A */

#define PIPEADSL		0x70000

#define PIPEACONF		0x70008

drivers/gpu/drm/i915/intel_display.c

+14 −1
Original line number Diff line number Diff line
@@ -3195,7 +3195,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, 
		 * appropriately here, but we need to look more thoroughly into how

		 * panels behave in the two modes.

		 */



		/* set the dithering flag */

		if (IS_I965G(dev)) {

			if (dev_priv->lvds_dither) {

				if (IS_IRONLAKE(dev))

					pipeconf |= PIPE_ENABLE_DITHER;

				else

					lvds |= LVDS_ENABLE_DITHER;

			} else {

				if (IS_IRONLAKE(dev))

					pipeconf &= ~PIPE_ENABLE_DITHER;

				else

					lvds &= ~LVDS_ENABLE_DITHER;

			}

		}

		I915_WRITE(lvds_reg, lvds);

		I915_READ(lvds_reg);

	}