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Commit 86ebb015 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cnl: WaDisableI2mCycleOnWRPort 



On CNL B0 stepping GAM is not able to detect some deadlock
condition and then rise the rise the gam_coh_flush.

WA database and spec both mentions to set 4AB8[24]=1 as
workaround. Although register offset 0x4AB8 is not
documented for any platform.

References: HSD#1945815, BSID#1112

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230751.21047-1-rodrigo.vivi@intel.com
parent 392572fe

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -2373,6 +2373,7 @@ enum i915_power_well_id { 




#define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)

#define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)

#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1<<28)

#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1<<28)

#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1<<24)





#if 0

#if 0

#define PRB0_TAIL	_MMIO(0x2030)

#define PRB0_TAIL	_MMIO(0x2030)

drivers/gpu/drm/i915/intel_engine_cs.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -1070,6 +1070,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) 
	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *dev_priv = engine->i915;

	int ret;

	int ret;





	/* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */

	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))

		WA_SET_BIT(GAMT_CHKN_BIT_REG,

			   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);



	/* WaForceContextSaveRestoreNonCoherent:cnl */

	/* WaForceContextSaveRestoreNonCoherent:cnl */

	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,

	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,

			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);

			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);