drm/nouveau/fb: merge fb/vram and port to subdev interfaces (861d2107) · Commits · e / devices / android_kernel_teracube_mt6765

drivers/gpu/drm/nouveau/Makefile

+3 −2

drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -163,7 +163,7 @@ nv40_fifo_init(struct drm_device *dev, int engine)
	break;		break;
	default:		default:
	nv_wr32(dev, 0x002230, 0x00000000);		nv_wr32(dev, 0x002230, 0x00000000);
	nv_wr32(dev, 0x002220, ((dev_priv->vram_size - 512 * 1024 +		nv_wr32(dev, 0x002220, ((nvfb_vram_size(dev) - 512 * 1024 +
	dev_priv->ramfc->pinst) >> 16) \|		dev_priv->ramfc->pinst) >> 16) \|
	0x00030000);		0x00030000);
	break;		break;

drivers/gpu/drm/nouveau/core/engine/graph/nv10.c

+1 −3

Original line number	Original line	Diff line number	Diff line
	@@ -895,9 +895,7 @@ nv10_graph_context_del(struct nouveau_channel *chan, int engine)
	static void		static void
	nv10_graph_set_tile_region(struct drm_device *dev, int i)		nv10_graph_set_tile_region(struct drm_device *dev, int i)
	{		{
	struct drm_nouveau_private *dev_priv = dev->dev_private;		struct nouveau_fb_tile *tile = nvfb_tile(dev, i);
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), tile->limit);		nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), tile->limit);
	nv_wr32(dev, NV10_PGRAPH_TSIZE(i), tile->pitch);		nv_wr32(dev, NV10_PGRAPH_TSIZE(i), tile->pitch);
	nv_wr32(dev, NV10_PGRAPH_TILE(i), tile->addr);		nv_wr32(dev, NV10_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/core/engine/graph/nv20.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -472,7 +472,7 @@ static void
	nv20_graph_set_tile_region(struct drm_device *dev, int i)		nv20_graph_set_tile_region(struct drm_device *dev, int i)
	{		{
	struct drm_nouveau_private *dev_priv = dev->dev_private;		struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];		struct nouveau_fb_tile *tile = nvfb_tile(dev, i);

	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/core/engine/graph/nv40.c

+2 −3

Original line number	Original line	Diff line number	Diff line
	@@ -125,7 +125,7 @@ static void
	nv40_graph_set_tile_region(struct drm_device *dev, int i)		nv40_graph_set_tile_region(struct drm_device *dev, int i)
	{		{
	struct drm_nouveau_private *dev_priv = dev->dev_private;		struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];		struct nouveau_fb_tile *tile = nvfb_tile(dev, i);

	switch (dev_priv->chipset) {		switch (dev_priv->chipset) {
	case 0x40:		case 0x40:
	@@ -178,7 +178,6 @@ nv40_graph_init(struct drm_device *dev, int engine)
	{		{
	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);		struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
	struct drm_nouveau_private *dev_priv = dev->dev_private;		struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	uint32_t vramsz;		uint32_t vramsz;
	int i, j;		int i, j;

	@@ -280,7 +279,7 @@ nv40_graph_init(struct drm_device *dev, int engine)
	}		}

	/* Turn all the tiling regions off. */		/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->num_tiles; i++)		for (i = 0; i < nvfb_tile_nr(dev); i++)
	nv40_graph_set_tile_region(dev, i);		nv40_graph_set_tile_region(dev, i);

	/* begin RAM config */		/* begin RAM config */

Original line number	Original line	Diff line number	Diff line
	@@ -8,6 +8,7 @@ ccflags-y += -I$(src)

	nouveau-y := core/core/client.o		nouveau-y := core/core/client.o
	nouveau-y += core/core/engine.o		nouveau-y += core/core/engine.o
			nouveau-y += core/core/enum.o
	nouveau-y += core/core/handle.o		nouveau-y += core/core/handle.o
	nouveau-y += core/core/mm.o		nouveau-y += core/core/mm.o
	nouveau-y += core/core/namedb.o		nouveau-y += core/core/namedb.o
	@@ -50,6 +51,7 @@ nouveau-y += core/subdev/devinit/nv10.o
	nouveau-y += core/subdev/devinit/nv1a.o		nouveau-y += core/subdev/devinit/nv1a.o
	nouveau-y += core/subdev/devinit/nv20.o		nouveau-y += core/subdev/devinit/nv20.o
	nouveau-y += core/subdev/devinit/nv50.o		nouveau-y += core/subdev/devinit/nv50.o
			nouveau-y += core/subdev/fb/base.o
	nouveau-y += core/subdev/fb/nv04.o		nouveau-y += core/subdev/fb/nv04.o
	nouveau-y += core/subdev/fb/nv10.o		nouveau-y += core/subdev/fb/nv10.o
	nouveau-y += core/subdev/fb/nv20.o		nouveau-y += core/subdev/fb/nv20.o
	@@ -57,8 +59,6 @@ nouveau-y += core/subdev/fb/nv30.o
	nouveau-y += core/subdev/fb/nv40.o		nouveau-y += core/subdev/fb/nv40.o
	nouveau-y += core/subdev/fb/nv50.o		nouveau-y += core/subdev/fb/nv50.o
	nouveau-y += core/subdev/fb/nvc0.o		nouveau-y += core/subdev/fb/nvc0.o
	nouveau-y += core/subdev/fb/nv50_vram.o
	nouveau-y += core/subdev/fb/nvc0_vram.o
	nouveau-y += core/subdev/gpio/base.o		nouveau-y += core/subdev/gpio/base.o
	nouveau-y += core/subdev/gpio/nv10.o		nouveau-y += core/subdev/gpio/nv10.o
	nouveau-y += core/subdev/gpio/nv50.o		nouveau-y += core/subdev/gpio/nv50.o
	@@ -69,6 +69,7 @@ nouveau-y += core/subdev/i2c/bit.o
	nouveau-y += core/subdev/instmem/nv04.o		nouveau-y += core/subdev/instmem/nv04.o
	nouveau-y += core/subdev/instmem/nv50.o		nouveau-y += core/subdev/instmem/nv50.o
	nouveau-y += core/subdev/instmem/nvc0.o		nouveau-y += core/subdev/instmem/nvc0.o
			nouveau-y += core/subdev/ltcg/nvc0.o
	nouveau-y += core/subdev/mc/base.o		nouveau-y += core/subdev/mc/base.o
	nouveau-y += core/subdev/mc/nv04.o		nouveau-y += core/subdev/mc/nv04.o
	nouveau-y += core/subdev/mc/nv44.o		nouveau-y += core/subdev/mc/nv44.o