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Commit 840f4bfb authored by Laszlo Ersek's avatar Laszlo Ersek Committed by Marc Zyngier
Browse files

arm, arm64: KVM: allow forced dcache flush on page faults 



To allow handling of incoherent memslots in a subsequent patch, this
patch adds a paramater 'ipa_uncached' to cache_coherent_guest_page()
so that we can instruct it to flush the page's contents to DRAM even
if the guest has caching globally enabled.

Signed-off-by: default avatarLaszlo Ersek <lersek@redhat.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 1050dcda

arch/arm/include/asm/kvm_mmu.h

+3 −2
Original line number Diff line number Diff line
@@ -161,9 +161,10 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) 
}



static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,

					     unsigned long size)

					     unsigned long size,

					     bool ipa_uncached)

{

	if (!vcpu_has_cache_enabled(vcpu))

	if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)

		kvm_flush_dcache_to_poc((void *)hva, size);

	

	/*

arch/arm/kvm/mmu.c

+7 −2
Original line number Diff line number Diff line
@@ -852,6 +852,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
	struct vm_area_struct *vma;

	pfn_t pfn;

	pgprot_t mem_type = PAGE_S2;

	bool fault_ipa_uncached;



	write_fault = kvm_is_write_fault(vcpu);

	if (fault_status == FSC_PERM && !write_fault) {
@@ -918,6 +919,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
	if (!hugetlb && !force_pte)

		hugetlb = transparent_hugepage_adjust(&pfn, &fault_ipa);



	fault_ipa_uncached = false;



	if (hugetlb) {

		pmd_t new_pmd = pfn_pmd(pfn, mem_type);

		new_pmd = pmd_mkhuge(new_pmd);
@@ -925,7 +928,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
			kvm_set_s2pmd_writable(&new_pmd);

			kvm_set_pfn_dirty(pfn);

		}

		coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE);

		coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE,

					  fault_ipa_uncached);

		ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);

	} else {

		pte_t new_pte = pfn_pte(pfn, mem_type);
@@ -933,7 +937,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
			kvm_set_s2pte_writable(&new_pte);

			kvm_set_pfn_dirty(pfn);

		}

		coherent_cache_guest_page(vcpu, hva, PAGE_SIZE);

		coherent_cache_guest_page(vcpu, hva, PAGE_SIZE,

					  fault_ipa_uncached);

		ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte,

			pgprot_val(mem_type) == pgprot_val(PAGE_S2_DEVICE));

	}

arch/arm64/include/asm/kvm_mmu.h

+3 −2
Original line number Diff line number Diff line
@@ -243,9 +243,10 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) 
}



static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,

					     unsigned long size)

					     unsigned long size,

					     bool ipa_uncached)

{

	if (!vcpu_has_cache_enabled(vcpu))

	if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)

		kvm_flush_dcache_to_poc((void *)hva, size);



	if (!icache_is_aliasing()) {		/* PIPT */