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Commit 8317797c authored by Linus Walleij's avatar Linus Walleij
Browse files

mfd: add DB5500 PRCMU driver 



This adds the DB5500 PRCMU driver. Right now this one is pretty
restricted in functionality, exposing a simple interface to send
I2C messages.

Acked-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 3df57bcf

arch/arm/mach-ux500/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -12,6 +12,7 @@ menu "Ux500 SoC" 




config UX500_SOC_DB5500

config UX500_SOC_DB5500

	bool "DB5500"

	bool "DB5500"

	select MFD_DB5500_PRCMU





config UX500_SOC_DB8500

config UX500_SOC_DB8500

	bool "DB8500"

	bool "DB8500"

arch/arm/mach-ux500/cpu.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/io.h>

#include <linux/io.h>

#include <linux/clk.h>

#include <linux/clk.h>

#include <linux/mfd/db8500-prcmu.h>

#include <linux/mfd/db8500-prcmu.h>

#include <linux/mfd/db5500-prcmu.h>





#include <asm/cacheflush.h>

#include <asm/cacheflush.h>

#include <asm/hardware/cache-l2x0.h>

#include <asm/hardware/cache-l2x0.h>
@@ -49,6 +50,8 @@ void __init ux500_init_irq(void) 
	 * Init clocks here so that they are available for system timer

	 * Init clocks here so that they are available for system timer

	 * initialization.

	 * initialization.

	 */

	 */

	if (cpu_is_u5500())

		db5500_prcmu_early_init();

	if (cpu_is_u8500())

	if (cpu_is_u8500())

		prcmu_early_init();

		prcmu_early_init();

	clk_init();

	clk_init();

drivers/mfd/Kconfig

+10 −0
Original line number Original line Diff line number Diff line
@@ -585,6 +585,16 @@ config MFD_DB8500_PRCMU 
	  system controller running an XP70 microprocessor, which is accessed

	  system controller running an XP70 microprocessor, which is accessed

	  through a register map.

	  through a register map.





config MFD_DB5500_PRCMU

	bool "ST-Ericsson DB5500 Power Reset Control Management Unit"

	depends on UX500_SOC_DB5500

	select MFD_CORE

	help

	  Select this option to enable support for the DB5500 Power Reset

	  and Control Management Unit. This is basically an autonomous

	  system controller running an XP70 microprocessor, which is accessed

	  through a register map.



config MFD_CS5535

config MFD_CS5535

	tristate "Support for CS5535 and CS5536 southbridge core functions"

	tristate "Support for CS5535 and CS5536 southbridge core functions"

	select MFD_CORE

	select MFD_CORE

drivers/mfd/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -79,6 +79,7 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o 
obj-$(CONFIG_MFD_DB8500_PRCMU)	+= db8500-prcmu.o

obj-$(CONFIG_MFD_DB8500_PRCMU)	+= db8500-prcmu.o

# ab8500-i2c need to come after db8500-prcmu (which provides the channel)

# ab8500-i2c need to come after db8500-prcmu (which provides the channel)

obj-$(CONFIG_AB8500_I2C_CORE)	+= ab8500-i2c.o

obj-$(CONFIG_AB8500_I2C_CORE)	+= ab8500-i2c.o

obj-$(CONFIG_MFD_DB5500_PRCMU)	+= db5500-prcmu.o

obj-$(CONFIG_MFD_TIMBERDALE)    += timberdale.o

obj-$(CONFIG_MFD_TIMBERDALE)    += timberdale.o

obj-$(CONFIG_PMIC_ADP5520)	+= adp5520.o

obj-$(CONFIG_PMIC_ADP5520)	+= adp5520.o

obj-$(CONFIG_LPC_SCH)		+= lpc_sch.o

obj-$(CONFIG_LPC_SCH)		+= lpc_sch.o

drivers/mfd/db5500-prcmu-regs.h

0 → 100644
+115 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) STMicroelectronics 2009

 * Copyright (C) ST-Ericsson SA 2010

 *

 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>

 * Author: Sundar Iyer <sundar.iyer@stericsson.com>

 *

 * License Terms: GNU General Public License v2

 *

 * PRCM Unit registers

 */



#ifndef __MACH_PRCMU_REGS_H

#define __MACH_PRCMU_REGS_H



#include <mach/hardware.h>



#define PRCM_ARM_PLLDIVPS	(_PRCMU_BASE + 0x118)

#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE		0x3f

#define PRCM_ARM_PLLDIVPS_MAX_MASK		0xf



#define PRCM_PLLARM_LOCKP       (_PRCMU_BASE + 0x0a8)

#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3	0x2



#define PRCM_ARM_CHGCLKREQ	(_PRCMU_BASE + 0x114)

#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ	0x1



#define PRCM_PLLARM_ENABLE	(_PRCMU_BASE + 0x98)

#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE	0x1

#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON	0x100



#define PRCM_ARMCLKFIX_MGT	(_PRCMU_BASE + 0x0)

#define PRCM_A9_RESETN_CLR	(_PRCMU_BASE + 0x1f4)

#define PRCM_A9_RESETN_SET	(_PRCMU_BASE + 0x1f0)

#define PRCM_ARM_LS_CLAMP	(_PRCMU_BASE + 0x30c)

#define PRCM_SRAM_A9		(_PRCMU_BASE + 0x308)



/* ARM WFI Standby signal register */

#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)

#define PRCM_IOCR		(_PRCMU_BASE + 0x310)

#define PRCM_IOCR_IOFORCE			0x1



/* CPU mailbox registers */

#define PRCM_MBOX_CPU_VAL	(_PRCMU_BASE + 0x0fc)

#define PRCM_MBOX_CPU_SET	(_PRCMU_BASE + 0x100)

#define PRCM_MBOX_CPU_CLR	(_PRCMU_BASE + 0x104)



/* Dual A9 core interrupt management unit registers */

#define PRCM_A9_MASK_REQ	(_PRCMU_BASE + 0x328)

#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ	0x1



#define PRCM_A9_MASK_ACK	(_PRCMU_BASE + 0x32c)

#define PRCM_ARMITMSK31TO0	(_PRCMU_BASE + 0x11c)

#define PRCM_ARMITMSK63TO32	(_PRCMU_BASE + 0x120)

#define PRCM_ARMITMSK95TO64	(_PRCMU_BASE + 0x124)

#define PRCM_ARMITMSK127TO96	(_PRCMU_BASE + 0x128)

#define PRCM_POWER_STATE_VAL	(_PRCMU_BASE + 0x25C)

#define PRCM_ARMITVAL31TO0	(_PRCMU_BASE + 0x260)

#define PRCM_ARMITVAL63TO32	(_PRCMU_BASE + 0x264)

#define PRCM_ARMITVAL95TO64	(_PRCMU_BASE + 0x268)

#define PRCM_ARMITVAL127TO96	(_PRCMU_BASE + 0x26C)



#define PRCM_HOSTACCESS_REQ	(_PRCMU_BASE + 0x334)

#define ARM_WAKEUP_MODEM	0x1



#define PRCM_ARM_IT1_CLEAR	(_PRCMU_BASE + 0x48C)

#define PRCM_ARM_IT1_VAL	(_PRCMU_BASE + 0x494)

#define PRCM_HOLD_EVT		(_PRCMU_BASE + 0x174)



#define PRCM_ITSTATUS0		(_PRCMU_BASE + 0x148)

#define PRCM_ITSTATUS1		(_PRCMU_BASE + 0x150)

#define PRCM_ITSTATUS2		(_PRCMU_BASE + 0x158)

#define PRCM_ITSTATUS3		(_PRCMU_BASE + 0x160)

#define PRCM_ITSTATUS4		(_PRCMU_BASE + 0x168)

#define PRCM_ITSTATUS5		(_PRCMU_BASE + 0x484)

#define PRCM_ITCLEAR5		(_PRCMU_BASE + 0x488)

#define PRCM_ARMIT_MASKXP70_IT	(_PRCMU_BASE + 0x1018)



/* System reset register */

#define PRCM_APE_SOFTRST	(_PRCMU_BASE + 0x228)



/* Level shifter and clamp control registers */

#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)

#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)



/* PRCMU clock/PLL/reset registers */

#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)

#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)

#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)

#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + 0x044)

#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + 0x064)

#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + 0x058)

#define PRCM_TVCLK_MGT             (_PRCMU_BASE + 0x07c)

#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)

#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)

#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)

#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)

#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)

#define PRCM_CLKOCR		   (_PRCMU_BASE + 0x1CC)



/* ePOD and memory power signal control registers */

#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)

#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)



/* Debug power control unit registers */

#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)



/* Miscellaneous unit registers */

#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)

#define PRCM_GPIOCR                (_PRCMU_BASE + 0x138)

#define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800

#define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1





#endif /* __MACH_PRCMU__REGS_H */