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Commit 8237eb94 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

* 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, microcode, AMD: Add microcode revision to /proc/cpuinfo
  x86, microcode: Correct microcode revision format
  coretemp: Get microcode revision from cpu_data
  x86, intel: Use c->microcode for Atom errata check
  x86, intel: Output microcode revision in /proc/cpuinfo
  x86, microcode: Don't request microcode from userspace unnecessarily

Fix up trivial conflicts in arch/x86/kernel/cpu/amd.c (conflict between
moving AMD BSP code to cpu_dev helper function and adding AMD microcode
revision to /proc/cpuinfo code)
parents cc21fe51 bcb80e53

arch/x86/include/asm/processor.h

+3 −1
Original line number Original line Diff line number Diff line
@@ -111,6 +111,7 @@ struct cpuinfo_x86 { 
	/* Index into per_cpu list: */

	/* Index into per_cpu list: */

	u16			cpu_index;

	u16			cpu_index;

#endif

#endif

	u32			microcode;

} __attribute__((__aligned__(SMP_CACHE_BYTES)));

} __attribute__((__aligned__(SMP_CACHE_BYTES)));





#define X86_VENDOR_INTEL	0

#define X86_VENDOR_INTEL	0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 
	      "=b" (*ebx),

	      "=b" (*ebx),

	      "=c" (*ecx),

	      "=c" (*ecx),

	      "=d" (*edx)

	      "=d" (*edx)

	    : "0" (*eax), "2" (*ecx));

	    : "0" (*eax), "2" (*ecx)

	    : "memory");

}

}





static inline void load_cr3(pgd_t *pgdir)

static inline void load_cr3(pgd_t *pgdir)

arch/x86/kernel/cpu/amd.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -441,6 +441,8 @@ static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) 




static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)

static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)

{

{

	u32 dummy;



	early_init_amd_mc(c);

	early_init_amd_mc(c);





	/*

	/*
@@ -470,6 +472,8 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 
			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);

			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);

	}

	}

#endif

#endif



	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);

}

}





static void __cpuinit init_amd(struct cpuinfo_x86 *c)

static void __cpuinit init_amd(struct cpuinfo_x86 *c)

arch/x86/kernel/cpu/intel.c

+13 −11
Original line number Original line Diff line number Diff line
@@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
		(c->x86 == 0x6 && c->x86_model >= 0x0e))

		(c->x86 == 0x6 && c->x86_model >= 0x0e))

		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);





	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {

		unsigned lower_word;



		wrmsr(MSR_IA32_UCODE_REV, 0, 0);

		/* Required by the SDM */

		sync_core();

		rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);

	}



	/*

	/*

	 * Atom erratum AAE44/AAF40/AAG38/AAH41:

	 * Atom erratum AAE44/AAF40/AAG38/AAH41:

	 *

	 *
@@ -55,18 +64,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
	 * need the microcode to have already been loaded... so if it is

	 * need the microcode to have already been loaded... so if it is

	 * not, recommend a BIOS update and disable large pages.

	 * not, recommend a BIOS update and disable large pages.

	 */

	 */

	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {

	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&

		u32 ucode, junk;

	    c->microcode < 0x20e) {



		wrmsr(MSR_IA32_UCODE_REV, 0, 0);

		sync_core();

		rdmsr(MSR_IA32_UCODE_REV, junk, ucode);



		if (ucode < 0x20e) {

		printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");

		printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");

		clear_cpu_cap(c, X86_FEATURE_PSE);

		clear_cpu_cap(c, X86_FEATURE_PSE);

	}

	}

	}





#ifdef CONFIG_X86_64

#ifdef CONFIG_X86_64

	set_cpu_cap(c, X86_FEATURE_SYSENTER32);

	set_cpu_cap(c, X86_FEATURE_SYSENTER32);

arch/x86/kernel/cpu/mcheck/mce.c

+7 −2
Original line number Original line Diff line number Diff line
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m) 
		pr_cont("MISC %llx ", m->misc);

		pr_cont("MISC %llx ", m->misc);





	pr_cont("\n");

	pr_cont("\n");

	pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",

	/*

		m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);

	 * Note this output is parsed by external tools and old fields

	 * should not be changed.

	 */

	pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",

		m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,

		cpu_data(m->extcpu).microcode);





	/*

	/*

	 * Print out human-readable details about the MCE error,

	 * Print out human-readable details about the MCE error,

arch/x86/kernel/cpu/proc.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		seq_printf(m, "stepping\t: %d\n", c->x86_mask);

		seq_printf(m, "stepping\t: %d\n", c->x86_mask);

	else

	else

		seq_printf(m, "stepping\t: unknown\n");

		seq_printf(m, "stepping\t: unknown\n");

	if (c->microcode)

		seq_printf(m, "microcode\t: 0x%x\n", c->microcode);





	if (cpu_has(c, X86_FEATURE_TSC)) {

	if (cpu_has(c, X86_FEATURE_TSC)) {

		unsigned int freq = cpufreq_quick_get(cpu);

		unsigned int freq = cpufreq_quick_get(cpu);