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Commit 815ed6fc authored by Tushar Behera's avatar Tushar Behera Committed by Kukjin Kim
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ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN 



Framebuffer driver needs to fetch the video data during the rising
edge of the VCLK. Otherwise, there are some glitches in the LCD
display.

Signed-off-by: default avatarTushar Behera <tushar.behera@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 6e11e0bd

arch/arm/mach-exynos/mach-origen.c

+2 −1
Original line number Diff line number Diff line
@@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = { 
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {

	.win[0]		= &origen_fb_win0,

	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,

	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,

	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |

				VIDCON1_INV_VCLK,

	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,

};