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Commit 7e95c548 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'next/dt' into HEAD 

Conflicts:
	Documentation/devicetree/bindings/usb/platform-uhci.txt
	arch/arm/mach-vt8500/bv07.c
	arch/arm/mach-vt8500/devices-vt8500.c
	arch/arm/mach-vt8500/devices-wm8505.c
	arch/arm/mach-vt8500/devices.c
	arch/arm/mach-vt8500/devices.h
	arch/arm/mach-vt8500/wm8505_7in.c
parents 6d55d596 99261fba

Documentation/devicetree/bindings/arm/mrvl/tauros2.txt

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* Marvell Tauros2 Cache



Required properties:

- compatible : Should be "marvell,tauros2-cache".

- marvell,tauros2-cache-features : Specify the features supported for the

  tauros2 cache.

  The features including

    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)

    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)

  The definition can be found at

  arch/arm/include/asm/hardware/cache-tauros2.h



Example:

	L2: l2-cache {

		compatible = "marvell,tauros2-cache";

		marvell,tauros2-cache-features = <0x3>;

	};

Documentation/devicetree/bindings/arm/msm/timer.txt

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* MSM Timer



Properties:



- compatible : Should at least contain "qcom,msm-timer". More specific

  properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general

  purpose timer and a debug timer respectively.



- interrupts : Interrupt indicating a match event.



- reg : Specifies the base address of the timer registers. The second region

  specifies an optional register used to configure the clock divider.



- clock-frequency : The frequency of the timer in Hz.



Optional:



- cpu-offset : per-cpu offset used when the timer is accessed without the

  CPU remapping facilities. The offset is cpu-offset * cpu-nr.



Example:



       timer@200a004 {

               compatible = "qcom,msm-gpt", "qcom,msm-timer";

               interrupts = <1 2 0x301>;

               reg = <0x0200a004 0x10>;

               clock-frequency = <32768>;

               cpu-offset = <0x40000>;

       };



       timer@200a024 {

               compatible = "qcom,msm-dgt", "qcom,msm-timer";

               interrupts = <1 3 0x301>;

               reg = <0x0200a024 0x10>,

                     <0x0200a034 0x4>;

               clock-frequency = <6750000>;

               cpu-offset = <0x40000>;

       };

Documentation/devicetree/bindings/arm/omap/omap.txt

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@@ -36,6 +36,9 @@ Boards: 
- OMAP3 BeagleBoard : Low cost community board

  compatible = "ti,omap3-beagle", "ti,omap3"



- OMAP3 Tobi with Overo : Commercial expansion board with daughter board

  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"



- OMAP4 SDP : Software Developement Board

  compatible = "ti,omap4-sdp", "ti,omap4430"

Documentation/devicetree/bindings/arm/vt8500.txt

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VIA/Wondermedia VT8500 Platforms Device Tree Bindings

---------------------------------------



Boards with the VIA VT8500 SoC shall have the following properties:

Required root node property:

compatible = "via,vt8500";



Boards with the Wondermedia WM8505 SoC shall have the following properties:

Required root node property:

compatible = "wm,wm8505";



Boards with the Wondermedia WM8650 SoC shall have the following properties:

Required root node property:

compatible = "wm,wm8650";

Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt

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VIA/Wondermedia VT8500 Interrupt Controller

-----------------------------------------------------



Required properties:

- compatible : "via,vt8500-intc"

- reg : Should contain 1 register ranges(address and length)

- #interrupt-cells : should be <1>



Example:



	intc: interrupt-controller@d8140000 {

		compatible = "via,vt8500-intc";

		interrupt-controller;

		reg = <0xd8140000 0x10000>;

		#interrupt-cells = <1>;

	};