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Commit 7b7293ae authored by Geoff Levand's avatar Geoff Levand Committed by Will Deacon
Browse files

arm64: Fold proc-macros.S into assembler.h 



To allow the assembler macros defined in arch/arm64/mm/proc-macros.S to
be used outside the mm code move the contents of proc-macros.S to
asm/assembler.h.  Also, delete proc-macros.S, and fix up all references
to proc-macros.S.

Signed-off-by: default avatarGeoff Levand <geoff@infradead.org>
Acked-by: default avatarPavel Machek <pavel@ucw.cz>
[rebased, included dcache_by_line_op]
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 6a1f5471

arch/arm64/include/asm/assembler.h

+81 −1
Original line number Diff line number Diff line 
/*

 * Based on arch/arm/include/asm/assembler.h

 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S

 *

 * Copyright (C) 1996-2000 Russell King

 * Copyright (C) 2012 ARM Ltd.
@@ -23,6 +23,8 @@ 
#ifndef __ASM_ASSEMBLER_H

#define __ASM_ASSEMBLER_H



#include <asm/asm-offsets.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>

#include <asm/thread_info.h>
@@ -199,6 +201,84 @@ lr .req x30 // link register 
	add	\reg, \reg, \tmp

	.endm



/*

 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)

 */

	.macro	vma_vm_mm, rd, rn

	ldr	\rd, [\rn, #VMA_VM_MM]

	.endm



/*

 * mmid - get context id from mm pointer (mm->context.id)

 */

	.macro	mmid, rd, rn

	ldr	\rd, [\rn, #MM_CONTEXT_ID]

	.endm



/*

 * dcache_line_size - get the minimum D-cache line size from the CTR register.

 */

	.macro	dcache_line_size, reg, tmp

	mrs	\tmp, ctr_el0			// read CTR

	ubfm	\tmp, \tmp, #16, #19		// cache line size encoding

	mov	\reg, #4			// bytes per word

	lsl	\reg, \reg, \tmp		// actual cache line size

	.endm



/*

 * icache_line_size - get the minimum I-cache line size from the CTR register.

 */

	.macro	icache_line_size, reg, tmp

	mrs	\tmp, ctr_el0			// read CTR

	and	\tmp, \tmp, #0xf		// cache line size encoding

	mov	\reg, #4			// bytes per word

	lsl	\reg, \reg, \tmp		// actual cache line size

	.endm



/*

 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map

 */

	.macro	tcr_set_idmap_t0sz, valreg, tmpreg

#ifndef CONFIG_ARM64_VA_BITS_48

	ldr_l	\tmpreg, idmap_t0sz

	bfi	\valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH

#endif

	.endm



/*

 * Macro to perform a data cache maintenance for the interval

 * [kaddr, kaddr + size)

 *

 * 	op:		operation passed to dc instruction

 * 	domain:		domain used in dsb instruciton

 * 	kaddr:		starting virtual address of the region

 * 	size:		size of the region

 * 	Corrupts:	kaddr, size, tmp1, tmp2

 */

	.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2

	dcache_line_size \tmp1, \tmp2

	add	\size, \kaddr, \size

	sub	\tmp2, \tmp1, #1

	bic	\kaddr, \kaddr, \tmp2

9998:	dc	\op, \kaddr

	add	\kaddr, \kaddr, \tmp1

	cmp	\kaddr, \size

	b.lo	9998b

	dsb	\domain

	.endm



/*

 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present

 */

	.macro	reset_pmuserenr_el0, tmpreg

	mrs	\tmpreg, id_aa64dfr0_el1	// Check ID_AA64DFR0_EL1 PMUVer

	sbfx	\tmpreg, \tmpreg, #8, #4

	cmp	\tmpreg, #1			// Skip if no PMU present

	b.lt	9000f

	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0

9000:

	.endm



/*

 * Annotate a function as position independent, i.e., safe to be called before

 * the kernel virtual mapping is activated.

arch/arm64/mm/cache.S

+0 −2
Original line number Diff line number Diff line
@@ -24,8 +24,6 @@ 
#include <asm/cpufeature.h>

#include <asm/alternative.h>



#include "proc-macros.S"



/*

 *	flush_icache_range(start,end)

 *

arch/arm64/mm/proc-macros.S

deleted100644 → 0
+0 −98
Original line number Diff line number Diff line 
/*

 * Based on arch/arm/mm/proc-macros.S

 *

 * Copyright (C) 2012 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <asm/asm-offsets.h>

#include <asm/thread_info.h>



/*

 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)

 */

	.macro	vma_vm_mm, rd, rn

	ldr	\rd, [\rn, #VMA_VM_MM]

	.endm



/*

 * mmid - get context id from mm pointer (mm->context.id)

 */

	.macro	mmid, rd, rn

	ldr	\rd, [\rn, #MM_CONTEXT_ID]

	.endm



/*

 * dcache_line_size - get the minimum D-cache line size from the CTR register.

 */

	.macro	dcache_line_size, reg, tmp

	mrs	\tmp, ctr_el0			// read CTR

	ubfm	\tmp, \tmp, #16, #19		// cache line size encoding

	mov	\reg, #4			// bytes per word

	lsl	\reg, \reg, \tmp		// actual cache line size

	.endm



/*

 * icache_line_size - get the minimum I-cache line size from the CTR register.

 */

	.macro	icache_line_size, reg, tmp

	mrs	\tmp, ctr_el0			// read CTR

	and	\tmp, \tmp, #0xf		// cache line size encoding

	mov	\reg, #4			// bytes per word

	lsl	\reg, \reg, \tmp		// actual cache line size

	.endm



/*

 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map

 */

	.macro	tcr_set_idmap_t0sz, valreg, tmpreg

#ifndef CONFIG_ARM64_VA_BITS_48

	ldr_l	\tmpreg, idmap_t0sz

	bfi	\valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH

#endif

	.endm



/*

 * Macro to perform a data cache maintenance for the interval

 * [kaddr, kaddr + size)

 *

 * 	op:		operation passed to dc instruction

 * 	domain:		domain used in dsb instruciton

 * 	kaddr:		starting virtual address of the region

 * 	size:		size of the region

 * 	Corrupts: 	kaddr, size, tmp1, tmp2

 */

	.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2

	dcache_line_size \tmp1, \tmp2

	add	\size, \kaddr, \size

	sub	\tmp2, \tmp1, #1

	bic	\kaddr, \kaddr, \tmp2

9998:	dc	\op, \kaddr

	add	\kaddr, \kaddr, \tmp1

	cmp	\kaddr, \size

	b.lo	9998b

	dsb	\domain

	.endm



/*

 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present

 */

	.macro	reset_pmuserenr_el0, tmpreg

	mrs	\tmpreg, id_aa64dfr0_el1	// Check ID_AA64DFR0_EL1 PMUVer

	sbfx	\tmpreg, \tmpreg, #8, #4

	cmp	\tmpreg, #1			// Skip if no PMU present

	b.lt	9000f

	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0

9000:

	.endm

arch/arm64/mm/proc.S

+0 −3
Original line number Diff line number Diff line
@@ -23,13 +23,10 @@ 
#include <asm/assembler.h>

#include <asm/asm-offsets.h>

#include <asm/hwcap.h>

#include <asm/pgtable-hwdef.h>

#include <asm/pgtable.h>

#include <asm/cpufeature.h>

#include <asm/alternative.h>



#include "proc-macros.S"



#ifdef CONFIG_ARM64_64K_PAGES

#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K

#elif defined(CONFIG_ARM64_16K_PAGES)