Merge branch 'next/dt-gscaler' of... (78901d05) · Commits · e / devices / android_kernel_teracube_mt6765

Documentation/devicetree/bindings/media/exynos5-gsc.txt

0 → 100644

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			* Samsung Exynos5 G-Scaler device

			G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs.

			Required properties:
			- compatible: should be "samsung,exynos5-gsc"
			- reg: should contain G-Scaler physical address location and length.
			- interrupts: should contain G-Scaler interrupt number

			Example:

			gsc_0: gsc@0x13e00000 {
			compatible = "samsung,exynos5-gsc";
			reg = <0x13e00000 0x1000>;
			interrupts = <0 85 0>;
			};

			Aliases:
			Each G-Scaler node should have a numbered alias in the aliases node,
			in the form of gscN, N = 0...3. G-Scaler driver uses these aliases
			to retrieve the device IDs using "of_alias_get_id()" call.

			Example:

			aliases {
			gsc0 =&gsc_0;
			gsc1 =&gsc_1;
			gsc2 =&gsc_2;
			gsc3 =&gsc_3;
			};

arch/arm/boot/dts/exynos5250.dtsi

+28 −0

Original line number	Original line	Diff line number	Diff line
	@@ -27,6 +27,10 @@
	spi0 = &spi_0;		spi0 = &spi_0;
	spi1 = &spi_1;		spi1 = &spi_1;
	spi2 = &spi_2;		spi2 = &spi_2;
			gsc0 = &gsc_0;
			gsc1 = &gsc_1;
			gsc2 = &gsc_2;
			gsc3 = &gsc_3;
	};		};

	gic:interrupt-controller@10481000 {		gic:interrupt-controller@10481000 {
	@@ -460,4 +464,28 @@
	#gpio-cells = <4>;		#gpio-cells = <4>;
	};		};
	};		};

			gsc_0: gsc@0x13e00000 {
			compatible = "samsung,exynos5-gsc";
			reg = <0x13e00000 0x1000>;
			interrupts = <0 85 0>;
			};

			gsc_1: gsc@0x13e10000 {
			compatible = "samsung,exynos5-gsc";
			reg = <0x13e10000 0x1000>;
			interrupts = <0 86 0>;
			};

			gsc_2: gsc@0x13e20000 {
			compatible = "samsung,exynos5-gsc";
			reg = <0x13e20000 0x1000>;
			interrupts = <0 87 0>;
			};

			gsc_3: gsc@0x13e30000 {
			compatible = "samsung,exynos5-gsc";
			reg = <0x13e30000 0x1000>;
			interrupts = <0 88 0>;
			};
	};		};

arch/arm/mach-exynos/clock-exynos5.c

+86 −0

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	@@ -552,6 +552,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
	};		};

			static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
			.clk = {
			.name = "mout_aclk_300_gscl_mid",
			},
			.sources = &exynos5_clkset_aclk,
			.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
			};

			static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
			[0] = &exynos5_clk_sclk_vpll.clk,
			[1] = &exynos5_clk_mout_cpll.clk,
			};

			static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
			.sources = exynos5_clkset_aclk_300_mid1_list,
			.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
			};

			static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
			.clk = {
			.name = "mout_aclk_300_gscl_mid1",
			},
			.sources = &exynos5_clkset_aclk_300_gscl_mid1,
			.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
			};

			static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
			[0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
			[1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
			};

			static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
			.sources = exynos5_clkset_aclk_300_gscl_list,
			.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
			};

			static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
			.clk = {
			.name = "mout_aclk_300_gscl",
			},
			.sources = &exynos5_clkset_aclk_300_gscl,
			.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
			};

			static struct clk *exynos5_clk_src_gscl_300_list[] = {
			[0] = &clk_ext_xtal_mux,
			[1] = &exynos5_clk_mout_aclk_300_gscl.clk,
			};

			static struct clksrc_sources exynos5_clk_src_gscl_300 = {
			.sources = exynos5_clk_src_gscl_300_list,
			.nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
			};

			static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
			.clk = {
			.name = "aclk_300_gscl",
			},
			.sources = &exynos5_clk_src_gscl_300,
			.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
			};

	static struct clk exynos5_init_clocks_off[] = {		static struct clk exynos5_init_clocks_off[] = {
	{		{
	.name = "timers",		.name = "timers",
	@@ -763,6 +825,26 @@ static struct clk exynos5_init_clocks_off[] = {
	.parent = &exynos5_clk_aclk_66.clk,		.parent = &exynos5_clk_aclk_66.clk,
	.enable = exynos5_clk_ip_peric_ctrl,		.enable = exynos5_clk_ip_peric_ctrl,
	.ctrlbit = (1 << 18),		.ctrlbit = (1 << 18),
			}, {
			.name = "gscl",
			.devname = "exynos-gsc.0",
			.enable = exynos5_clk_ip_gscl_ctrl,
			.ctrlbit = (1 << 0),
			}, {
			.name = "gscl",
			.devname = "exynos-gsc.1",
			.enable = exynos5_clk_ip_gscl_ctrl,
			.ctrlbit = (1 << 1),
			}, {
			.name = "gscl",
			.devname = "exynos-gsc.2",
			.enable = exynos5_clk_ip_gscl_ctrl,
			.ctrlbit = (1 << 2),
			}, {
			.name = "gscl",
			.devname = "exynos-gsc.3",
			.enable = exynos5_clk_ip_gscl_ctrl,
			.ctrlbit = (1 << 3),
	}, {		}, {
	.name = SYSMMU_CLOCK_NAME,		.name = SYSMMU_CLOCK_NAME,
	.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),		.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
	@@ -1225,6 +1307,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
	&exynos5_clk_aclk_266,		&exynos5_clk_aclk_266,
	&exynos5_clk_aclk_200,		&exynos5_clk_aclk_200,
	&exynos5_clk_aclk_166,		&exynos5_clk_aclk_166,
			&exynos5_clk_aclk_300_gscl,
			&exynos5_clk_mout_aclk_300_gscl,
			&exynos5_clk_mout_aclk_300_gscl_mid,
			&exynos5_clk_mout_aclk_300_gscl_mid1,
	&exynos5_clk_aclk_66_pre,		&exynos5_clk_aclk_66_pre,
	&exynos5_clk_aclk_66,		&exynos5_clk_aclk_66,
	&exynos5_clk_dout_mmc0,		&exynos5_clk_dout_mmc0,

arch/arm/mach-exynos/include/mach/map.h

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -121,6 +121,11 @@
	#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000		#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
	#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000		#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000

			#define EXYNOS5_PA_GSC0 0x13E00000
			#define EXYNOS5_PA_GSC1 0x13E10000
			#define EXYNOS5_PA_GSC2 0x13E20000
			#define EXYNOS5_PA_GSC3 0x13E30000

	#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000		#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
	#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000		#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
	#define EXYNOS5_PA_SYSMMU_2D 0x10A60000		#define EXYNOS5_PA_SYSMMU_2D 0x10A60000

arch/arm/mach-exynos/mach-exynos5-dt.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -56,6 +56,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),		OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),		OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),		OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
			OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
			"exynos-gsc.0", NULL),
			OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
			"exynos-gsc.1", NULL),
			OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
			"exynos-gsc.2", NULL),
			OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
			"exynos-gsc.3", NULL),
	{},		{},
	};		};