Commit 73053d97 authored Apr 17, 2013 by Rob Herring Committed by Olof Johansson Apr 18, 2013

ARM: highbank: fix cache flush ordering for cpu hotplug



The L1 data cache flush needs to be after highbank_set_cpu_jump call which
pollutes the cache with the l2x0_lock. This causes other cores to deadlock
waiting for the l2x0_lock. Moving the flush of the entire data cache after
highbank_set_cpu_jump fixes the problem. Use flush_cache_louis instead of
flush_cache_all are that is sufficient to flush only the L1 data cache.
flush_cache_louis did not exist when highbank_cpu_die was originally
written.

With PL310 errata 769419 enabled, a wmb is inserted into idle which takes
the l2x0_lock. This makes the problem much more easily hit and causes
reset to hang.

Reported-by: Paolo Pisati <p.pisati@gmail.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

parent 71bd98af

arch/arm/mach-highbank/hotplug.c

+4 −6

Original line number	Original line	Diff line number	Diff line
	@@ -28,13 +28,11 @@ extern void secondary_startup(void);
	*/		*/
	void __ref highbank_cpu_die(unsigned int cpu)		void __ref highbank_cpu_die(unsigned int cpu)
	{		{
	flush_cache_all();

	highbank_set_cpu_jump(cpu, phys_to_virt(0));		highbank_set_cpu_jump(cpu, phys_to_virt(0));

			flush_cache_louis();
	highbank_set_core_pwr();		highbank_set_core_pwr();

			while (1)
	cpu_do_idle();		cpu_do_idle();

	/* We should never return from idle */
	panic("highbank: cpu %d unexpectedly exit from shutdown\n", cpu);
	}		}