Merge branches 'iommu/fixes', 'arm/rockchip', 'arm/renesas', 'arm/smmu',...

			expediting.  Set to zero to disable automatic

			expediting.

	stack_guard_gap=	[MM]

			override the default stack gap protection. The value

			is in page units and it defines how many pages prior

			to (for stacks growing down) resp. after (for stacks

			growing up) the main stack are reserved for no other

			mapping. Default value is 256 pages.

	stacktrace	[FTRACE]

			Enabled the stack tracer on boot up.

| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |

| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |

| Cavium         | ThunderX SMMUv2 | #27704          | N/A                         |

| Cavium         | ThunderX2 SMMUv3| #74             | N/A                         |

| Cavium         | ThunderX2 SMMUv3| #126            | N/A                         |

|                |                 |                 |                             |

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

|                |                 |                 |                             |

| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |

| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

|                |                 |                 |                             |

| Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

- #clock-cells : must contain 1

- #reset-cells : must contain 1

For the PRCM CCUs on H3/A64, one more clock is needed:

For the PRCM CCUs on H3/A64, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator

Example for generic CCU:

r_ccu: clock@01f01400 {

	compatible = "allwinner,sun50i-a64-r-ccu";

	reg = <0x01f01400 0x100>;

	clocks = <&osc24M>, <&osc32k>, <&iosc>;

	clock-names = "hosc", "losc", "iosc";

	clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;

	clock-names = "hosc", "losc", "iosc", "pll-periph";

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Optional properties:

In order to use the GPIO lines in PWM mode, some additional optional

properties are required. Only Armada 370 and XP support these properties.

properties are required.

- compatible: Must contain "marvell,armada-370-xp-gpio"

- compatible: Must contain "marvell,armada-370-gpio"

- reg: an additional register set is needed, for the GPIO Blink

  Counter on/off registers.

		};

		gpio1: gpio@18140 {

			compatible = "marvell,armada-370-xp-gpio";

			compatible = "marvell,armada-370-gpio";

			reg = <0x18140 0x40>, <0x181c8 0x08>;

			reg-names = "gpio", "pwm";

			ngpios = <17>;

                      * "priq"      - PRI Queue not empty

                      * "cmdq-sync" - CMD_SYNC complete

                      * "gerror"    - Global Error activated

                      * "combined"  - The combined interrupt is optional,

				      and should only be provided if the

				      hardware supports just a single,

				      combined interrupt line.

				      If provided, then the combined interrupt

				      will be used in preference to any others.

- #iommu-cells      : See the generic IOMMU binding described in

                        devicetree/bindings/pci/pci-iommu.txt

- hisilicon,broken-prefetch-cmd

                    : Avoid sending CMD_PREFETCH_* commands to the SMMU.

- cavium,cn9900-broken-page1-regspace

                    : Replaces all page 1 offsets used for EVTQ_PROD/CONS,

		      PRIQ_PROD/CONS register access with page 0 offsets.

		      Set for Cavium ThunderX2 silicon that doesn't support

		      SMMU page1 register space.

** Example

        smmu@2b400000 {