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Commit 64c02720 authored by Xie XiuQi's avatar Xie XiuQi Committed by Catalin Marinas
Browse files

arm64: cpufeature: Detect CPU RAS Extentions 



ARM's v8.2 Extentions add support for Reliability, Availability and
Serviceability (RAS). On CPUs with these extensions system software
can use additional barriers to isolate errors and determine if faults
are pending. Add cpufeature detection.

Platform level RAS support may require additional firmware support.

Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
[Rebased added config option, reworded commit message]
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 7a00d68e

arch/arm64/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -1062,6 +1062,22 @@ config ARM64_PMEM 
	  operations if DC CVAP is not supported (following the behaviour of

	  DC CVAP itself if the system does not define a point of persistence).



config ARM64_RAS_EXTN

	bool "Enable support for RAS CPU Extensions"

	default y

	help

	  CPUs that support the Reliability, Availability and Serviceability

	  (RAS) Extensions, part of ARMv8.2 are able to track faults and

	  errors, classify them and report them to software.



	  On CPUs with these extensions system software can use additional

	  barriers to determine if faults are pending and read the

	  classification from a new set of registers.



	  Selecting this feature will allow the kernel to use these barriers

	  and access the new registers if the system supports the extension.

	  Platform RAS features may additionally depend on firmware support.



endmenu



config ARM64_SVE

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -44,7 +44,8 @@ 
#define ARM64_UNMAP_KERNEL_AT_EL0		23

#define ARM64_HARDEN_BRANCH_PREDICTOR		24

#define ARM64_HARDEN_BP_POST_GUEST_EXIT		25

#define ARM64_HAS_RAS_EXTN			26



#define ARM64_NCAPS				26

#define ARM64_NCAPS				27



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/sysreg.h

+2 −0
Original line number Diff line number Diff line
@@ -498,6 +498,7 @@ 
#define ID_AA64PFR0_CSV3_SHIFT		60

#define ID_AA64PFR0_CSV2_SHIFT		56

#define ID_AA64PFR0_SVE_SHIFT		32

#define ID_AA64PFR0_RAS_SHIFT		28

#define ID_AA64PFR0_GIC_SHIFT		24

#define ID_AA64PFR0_ASIMD_SHIFT		20

#define ID_AA64PFR0_FP_SHIFT		16
@@ -507,6 +508,7 @@ 
#define ID_AA64PFR0_EL0_SHIFT		0



#define ID_AA64PFR0_SVE			0x1

#define ID_AA64PFR0_RAS_V1		0x1

#define ID_AA64PFR0_FP_NI		0xf

#define ID_AA64PFR0_FP_SUPPORTED	0x0

#define ID_AA64PFR0_ASIMD_NI		0xf

arch/arm64/kernel/cpufeature.c

+13 −0
Original line number Diff line number Diff line
@@ -149,6 +149,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 
	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),

	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
@@ -1028,6 +1029,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.enable = sve_kernel_enable,

	},

#endif /* CONFIG_ARM64_SVE */

#ifdef CONFIG_ARM64_RAS_EXTN

	{

		.desc = "RAS Extension Support",

		.capability = ARM64_HAS_RAS_EXTN,

		.def_scope = SCOPE_SYSTEM,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64PFR0_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR0_RAS_SHIFT,

		.min_field_value = ID_AA64PFR0_RAS_V1,

	},

#endif /* CONFIG_ARM64_RAS_EXTN */

	{},

};