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Commit 638c201e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "This contains one i915 patch twice, as I merged it locally for
  testing, and then pulled some stuff in on top, and then Jani sent to
  me, I didn't think it was worth redoing all the merges of what I had
  tested.

  Summary:

   - amdgpu/radeon fixes for some more power management and VM races.

   - Two i915 fixes, one for the a recent regression, one another power
     management fix for skylake.

   - Two tegra dma mask fixes for a regression.

   - One ast fix for a typo I made transcribing the userspace driver,
     that I'd like to get into stable so I don't forget about it"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  gpu: host1x: Set DMA ops on device creation
  gpu: host1x: Set DMA mask
  drm/amdgpu: return from atombios_dp_get_dpcd only when error
  drm/amdgpu/cz: remove commented out call to enable vce pg
  drm/amdgpu/powerplay/cz: enable/disable vce dpm independent of vce pg
  drm/amdgpu/cz: enable/disable vce dpm even if vce pg is disabled
  drm/amdgpu/gfx8: specify which engine to wait before vm flush
  drm/amdgpu: apply gfx_v8 fixes to gfx_v7 as well
  drm/amd/powerplay: send event to notify powerplay all modules are initialized.
  drm/amd/powerplay: export AMD_PP_EVENT_COMPLETE_INIT task to amdgpu.
  drm/radeon/pm: update current crtc info after setting the powerstate
  drm/amdgpu/pm: update current crtc info after setting the powerstate
  drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
  drm/i915/skl: Fix power domain suspend sequence
  drm/ast: Fix incorrect register check for DRAM width
  drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
parents b80e8e28 26bae5e0

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

+1 −1
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ void amdgpu_connector_hotplug(struct drm_connector *connector) 
			} else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {

				/* Don't try to start link training before we

				 * have the dpcd */

				if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))

				if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))

					return;



				/* set it to OFF so that drm_helper_connector_dpms()

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+3 −3
Original line number Diff line number Diff line
@@ -649,9 +649,6 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) 
	/* update display watermarks based on new power state */

	amdgpu_display_bandwidth_update(adev);



	adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;

	adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;



	/* wait for the rings to drain */

	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {

		struct amdgpu_ring *ring = adev->rings[i];
@@ -670,6 +667,9 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) 
	/* update displays */

	amdgpu_dpm_display_configuration_changed(adev);



	adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;

	adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;



	if (adev->pm.funcs->force_performance_level) {

		if (adev->pm.dpm.thermal_active) {

			enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;

drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

+3 −1
Original line number Diff line number Diff line
@@ -143,8 +143,10 @@ static int amdgpu_pp_late_init(void *handle) 
					adev->powerplay.pp_handle);



#ifdef CONFIG_DRM_AMD_POWERPLAY

	if (adev->pp_enabled)

	if (adev->pp_enabled) {

		amdgpu_pm_sysfs_init(adev);

		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);

	}

#endif

	return ret;

}

drivers/gpu/drm/amd/amdgpu/cz_dpm.c

+2 −5
Original line number Diff line number Diff line
@@ -2202,8 +2202,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) 
							    AMD_PG_STATE_GATE);



				cz_enable_vce_dpm(adev, false);

				/* TODO: to figure out why vce can't be poweroff. */

				/* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */

				cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);

				pi->vce_power_gated = true;

			} else {

				cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
@@ -2226,10 +2225,8 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) 
		}

	} else { /*pi->caps_vce_pg*/

		cz_update_vce_dpm(adev);

		cz_enable_vce_dpm(adev, true);

		cz_enable_vce_dpm(adev, !gate);

	}



	return;

}



const struct amd_ip_funcs cz_dpm_ip_funcs = {

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+13 −0
Original line number Diff line number Diff line
@@ -3628,6 +3628,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 
					unsigned vm_id, uint64_t pd_addr)

{

	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);

	uint32_t seq = ring->fence_drv.sync_seq;

	uint64_t addr = ring->fence_drv.gpu_addr;



	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

	amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */

				 WAIT_REG_MEM_FUNCTION(3) | /* equal */

				 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */

	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq);

	amdgpu_ring_write(ring, 0xffffffff);

	amdgpu_ring_write(ring, 4); /* poll interval */



	if (usepfp) {

		/* synce CE with ME to prevent CE fetch CEIB before context switch done */

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));