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Commit 619f3bd2 authored by Kazuya Mizuguchi's avatar Kazuya Mizuguchi Committed by David S. Miller
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ravb: Document binding for r8a7795 SoC 



This patch updates the ravb binding to support the r8a7795 SoC by:
- Adding a compat string for the new hardware
- Adding 25 named interrupts to binding for the new SoC;
  older SoCs continue to use a single multiplexed interrupt

The example is also updated to reflect the r8a7795 as this is the
more complex case.

Based on work by Kazuya Mizuguchi and others.

Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e2dbb33a

Documentation/devicetree/bindings/net/renesas,ravb.txt

+62 −7
Original line number Original line Diff line number Diff line
@@ -6,8 +6,12 @@ interface contains. 
Required properties:

Required properties:

- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.

- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.

	      "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.

	      "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.

	      "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC.

- reg: offset and length of (1) the register block and (2) the stream buffer.

- reg: offset and length of (1) the register block and (2) the stream buffer.

- interrupts: interrupt specifier for the sole interrupt.

- interrupts: A list of interrupt-specifiers, one for each entry in

	      interrupt-names.

	      If interrupt-names is not present, an interrupt specifier

	      for a single muxed interrupt.

- phy-mode: see ethernet.txt file in the same directory.

- phy-mode: see ethernet.txt file in the same directory.

- phy-handle: see ethernet.txt file in the same directory.

- phy-handle: see ethernet.txt file in the same directory.

- #address-cells: number of address cells for the MDIO bus, must be equal to 1.

- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
@@ -18,6 +22,12 @@ Required properties: 
Optional properties:

Optional properties:

- interrupt-parent: the phandle for the interrupt controller that services

- interrupt-parent: the phandle for the interrupt controller that services

		    interrupts for this device.

		    interrupts for this device.

- interrupt-names: A list of interrupt names.

		   For the R8A7795 SoC this property is mandatory;

		   it should include one entry per channel, named "ch%u",

		   where %u is the channel number ranging from 0 to 24.

		   For other SoCs this property is optional; if present

		   it should contain "mux" for a single muxed interrupt.

- pinctrl-names: pin configuration state name ("default").

- pinctrl-names: pin configuration state name ("default").

- renesas,no-ether-link: boolean, specify when a board does not provide a proper

- renesas,no-ether-link: boolean, specify when a board does not provide a proper

			 AVB_LINK signal.

			 AVB_LINK signal.
@@ -27,13 +37,46 @@ Optional properties: 
Example:

Example:





	ethernet@e6800000 {

	ethernet@e6800000 {

		compatible = "renesas,etheravb-r8a7790";

		compatible = "renesas,etheravb-r8a7795";

		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

		reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;

		interrupt-parent = <&gic>;

		interrupt-parent = <&gic>;

		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

		clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;

			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

		phy-mode = "rmii";

			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "ch0", "ch1", "ch2", "ch3",

				  "ch4", "ch5", "ch6", "ch7",

				  "ch8", "ch9", "ch10", "ch11",

				  "ch12", "ch13", "ch14", "ch15",

				  "ch16", "ch17", "ch18", "ch19",

				  "ch20", "ch21", "ch22", "ch23",

				  "ch24";

		clocks = <&mstp8_clks R8A7795_CLK_ETHERAVB>;

		power-domains = <&cpg_clocks>;

		phy-mode = "rgmii-id";

		phy-handle = <&phy0>;

		phy-handle = <&phy0>;



		pinctrl-0 = <&ether_pins>;

		pinctrl-0 = <&ether_pins>;

		pinctrl-names = "default";

		pinctrl-names = "default";

		renesas,no-ether-link;

		renesas,no-ether-link;
@@ -41,8 +84,20 @@ Example: 
		#size-cells = <0>;

		#size-cells = <0>;





		phy0: ethernet-phy@0 {

		phy0: ethernet-phy@0 {

			rxc-skew-ps = <900>;

			rxdv-skew-ps = <0>;

			rxd0-skew-ps = <0>;

			rxd1-skew-ps = <0>;

			rxd2-skew-ps = <0>;

			rxd3-skew-ps = <0>;

			txc-skew-ps = <900>;

			txen-skew-ps = <0>;

			txd0-skew-ps = <0>;

			txd1-skew-ps = <0>;

			txd2-skew-ps = <0>;

			txd3-skew-ps = <0>;

			reg = <0>;

			reg = <0>;

			interrupt-parent = <&gpio2>;

			interrupt-parent = <&gpio2>;

			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;

			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

		};

		};

	};
 
	};