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Commit 615c16a9 authored by fred gao's avatar fred gao Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Refine virtual reset function 



during the emulation of virtual reset:
1. only reset the engine related mmio ending with MMIO
   offset Master_IRQ, not include display stuff.

2. fences are not required to set default
   value as well to prevent screen flicking.

this will fix the issue of Guest screen hang while running
Force tdr in Linux guest.

v2:
- only reset the engine related mmio. (Zhenyu & Zhiyuan)
v3:
- IMR/Ring mode registers are not save/restored. (Changbin)
v4:
- redefine the MMIO reset offset for easy understanding. (Zhenyu)
- pvinfo can be reset. (Zhenyu)
v5:
- add more comments for mmio reset. (Zhenyu)

Cc: Changbin Du <changbin.du@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Lv zhiyuan <zhiyuan.lv@intel.com>
Cc: Zhang Yulei <yulei.zhang@intel.com>
Signed-off-by: default avatarfred gao <fred.gao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 0811fa66

drivers/gpu/drm/i915/gvt/mmio.c

+20 −8
Original line number Diff line number Diff line
@@ -289,13 +289,15 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa, 
 * @vgpu: a vGPU

 *

 */

void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu)

void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)

{

	struct intel_gvt *gvt = vgpu->gvt;

	const struct intel_gvt_device_info *info = &gvt->device_info;

	void  *mmio = gvt->firmware.mmio;



	memcpy(vgpu->mmio.vreg, gvt->firmware.mmio, info->mmio_size);

	memcpy(vgpu->mmio.sreg, gvt->firmware.mmio, info->mmio_size);

	if (dmlr) {

		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);

		memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);



		vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
@@ -303,6 +305,16 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu) 
		vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;



		vgpu->mmio.disable_warn_untrack = false;

	} else {

#define GVT_GEN8_MMIO_RESET_OFFSET		(0x44200)

		/* only reset the engine related, so starting with 0x44200

		 * interrupt include DE,display mmio related will not be

		 * touched

		 */

		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);

		memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);

	}



}



/**
@@ -322,7 +334,7 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu) 


	vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;



	intel_vgpu_reset_mmio(vgpu);

	intel_vgpu_reset_mmio(vgpu, true);



	return 0;

}

drivers/gpu/drm/i915/gvt/mmio.h

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt); 
})



int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);

void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu);

void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);

void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);



int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);

drivers/gpu/drm/i915/gvt/vgpu.c

+7 −2
Original line number Diff line number Diff line
@@ -501,9 +501,14 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 


	/* full GPU reset or device model level reset */

	if (engine_mask == ALL_ENGINES || dmlr) {



		intel_vgpu_reset_gtt(vgpu, dmlr);



		/*fence will not be reset during virtual reset */

		if (dmlr)

			intel_vgpu_reset_resource(vgpu);

		intel_vgpu_reset_mmio(vgpu);



		intel_vgpu_reset_mmio(vgpu, dmlr);

		populate_pvinfo_page(vgpu);

		intel_vgpu_reset_display(vgpu);