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Commit 5fae4058 authored by Pannaga Bhushan's avatar Pannaga Bhushan Committed by Ben Dooks
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ARM: S5P: Fix the platform external interrupt issues. 



This patch does the following:

1. Corrects the common platform code for external interrupts for using the
   VIC mask/unmask bits also.
2. Moves the common defines related to external interrupt for plat-s5p
   to common files.
3. Based on the new common defines, corresponding changes are made in the
   affected platforms (S5P6440, S5P6442 and S5PC100).

Signed-off-by: default avatarPannaga Bhushan <p.bhushan@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent b1cdc467

arch/arm/mach-s5p6440/include/mach/irqs.h

+8 −1
Original line number Diff line number Diff line
@@ -72,7 +72,14 @@ 
#define S5P_IRQ_EINT_BASE	(S5P_IRQ_VIC1(31) + 6)



#define S5P_EINT(x)		((x) + S5P_IRQ_EINT_BASE)

#define IRQ_EINT(x)		S5P_EINT(x)



#define S5P_EINT_BASE1		(S5P_IRQ_EINT_BASE)

/*

 * S5P6440 has 0-15 external interrupts in group 0. Only these can be used

 * to wake up from sleep. If request is beyond this range, by mistake, a large

 * return value for an irq number should be indication of something amiss.

 */

#define S5P_EINT_BASE2		(0xf0000000)



/*

 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)

arch/arm/mach-s5p6442/include/mach/irqs.h

+3 −2
Original line number Diff line number Diff line
@@ -77,8 +77,9 @@ 


#define S5P_IRQ_EINT_BASE	(IRQ_VIC_END + 1)



#define IRQ_EINT(x)             ((x) < 16 ? S5P_IRQ_VIC0(x) : \

					(S5P_IRQ_EINT_BASE + (x)-16))

#define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))

#define S5P_EINT_BASE2		(S5P_IRQ_EINT_BASE)



/* Set the default NR_IRQS */



#define NR_IRQS 		(IRQ_EINT(31) + 1)

arch/arm/mach-s5pc100/include/mach/irqs.h

+0 −3
Original line number Diff line number Diff line
@@ -100,9 +100,6 @@ 
#define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))

#define S5P_EINT_BASE2		(IRQ_VIC_END + 1)



#define IRQ_EINT(x)		((x) < 16 ? S5P_IRQ_VIC0(x) : \

				 (S5P_EINT_BASE2 + (x) - 16))



#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)

#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))

arch/arm/mach-s5pv210/include/mach/irqs.h

+2 −12
Original line number Diff line number Diff line
@@ -118,22 +118,12 @@ 
#define IRQ_MDNIE3		S5P_IRQ_VIC3(8)

#define IRQ_VIC_END		S5P_IRQ_VIC3(31)



#define S5P_EINT_16_31_BASE	(IRQ_VIC_END + 1)



#define EINT_MODE		S3C_GPIO_SFN(0xf)



#define IRQ_EINT(x)		((x) < 16 ? ((x) + S5P_IRQ_VIC0(0)) \

					: ((x) + S5P_EINT_16_31_BASE))

#define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))

#define S5P_EINT_BASE2		(IRQ_VIC_END + 1)



/* Set the default NR_IRQS */



#define NR_IRQS			(IRQ_EINT(31) + 1)



#define EINT_GPIO_0(x)		S5PV210_GPH0(x)

#define EINT_GPIO_1(x)		S5PV210_GPH1(x)

#define EINT_GPIO_2(x)		S5PV210_GPH2(x)

#define EINT_GPIO_3(x)		S5PV210_GPH3(x)



/* Compatibility */

#define IRQ_LCD_FIFO		IRQ_LCD0

#define IRQ_LCD_VSYNC		IRQ_LCD1

arch/arm/mach-s5pv210/include/mach/regs-gpio.h

+9 −5
Original line number Diff line number Diff line
@@ -27,12 +27,9 @@ 
#define S5PV210_EINT30PEND		(S5P_VA_GPIO + 0xF40)

#define S5P_EINT_PEND(x)		(S5PV210_EINT30PEND + ((x) * 0x4))



#define eint_offset(irq)	((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) \

						: ((irq) - S5P_EINT_16_31_BASE))

#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)



#define EINT_REG_NR(x)			(eint_offset(x) >> 3)



#define eint_irq_to_bit(irq)		(1 << (eint_offset(irq) & 0x7))

#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))



/* values for S5P_EXTINT0 */

#define S5P_EXTINT_LOWLEV		(0x00)
@@ -41,4 +38,11 @@ 
#define S5P_EXTINT_RISEEDGE		(0x03)

#define S5P_EXTINT_BOTHEDGE		(0x04)



#define EINT_MODE		S3C_GPIO_SFN(0xf)



#define EINT_GPIO_0(x)		S5PV210_GPH0(x)

#define EINT_GPIO_1(x)		S5PV210_GPH1(x)

#define EINT_GPIO_2(x)		S5PV210_GPH2(x)

#define EINT_GPIO_3(x)		S5PV210_GPH3(x)



#endif /* __ASM_ARCH_REGS_GPIO_H */