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Commit 5e0fac63 authored by Ding Tianhong's avatar Ding Tianhong Committed by Jeff Kirsher
Browse files

net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag 



The ixgbe driver use the compile check to determine if it can
send TLPs to Root Port with the Relaxed Ordering Attribute set,
this is too inconvenient, now the new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING
has been added to the kernel and we could check the bit4 in the PCIe
Device Control register to determine whether we should use the Relaxed
Ordering Attributes or not, so use this new way in the ixgbe driver.

Signed-off-by: default avatarDing Tianhong <dingtianhong@huawei.com>
Acked-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent f4986d25

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+0 −22
Original line number Diff line number Diff line
@@ -175,31 +175,9 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 
 **/

static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)

{

#ifndef CONFIG_SPARC

	u32 regval;

	u32 i;

#endif

	s32 ret_val;



	ret_val = ixgbe_start_hw_generic(hw);



#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	for (i = 0; ((i < hw->mac.max_tx_queues) &&

	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {

		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));

		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);

	}



	for (i = 0; ((i < hw->mac.max_rx_queues) &&

	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {

		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));

		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |

			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}

#endif

	if (ret_val)

		return ret_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+0 −19
Original line number Diff line number Diff line
@@ -366,25 +366,6 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 
	}

	IXGBE_WRITE_FLUSH(hw);



#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {

		u32 regval;



		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));

		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);

	}



	for (i = 0; i < hw->mac.max_rx_queues; i++) {

		u32 regval;



		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));

		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |

			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}

#endif

	return 0;

}