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Commit 5af23440 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'char-misc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char / misc driver updates from Greg KH:
 "Here's the big char and misc driver update for 4.7-rc1.

  Lots of different tiny driver subsystems have updates here with new
  drivers and functionality.  Details in the shortlog.

  All have been in linux-next with no reported issues for a while"

* tag 'char-misc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (125 commits)
  mcb: Delete num_cells variable which is not required
  mcb: Fixed bar number assignment for the gdd
  mcb: Replace ioremap and request_region with the devm version
  mcb: Implement bus->dev.release callback
  mcb: export bus information via sysfs
  mcb: Correctly initialize the bus's device
  mei: bus: call mei_cl_read_start under device lock
  coresight: etb10: adjust read pointer only when needed
  coresight: configuring ETF in FIFO mode when acting as link
  coresight: tmc: implementing TMC-ETF AUX space API
  coresight: moving struct cs_buffers to header file
  coresight: tmc: keep track of memory width
  coresight: tmc: make sysFS and Perf mode mutually exclusive
  coresight: tmc: dump system memory content only when needed
  coresight: tmc: adding mode of operation for link/sinks
  coresight: tmc: getting rid of multiple read access
  coresight: tmc: allocating memory when needed
  coresight: tmc: making prepare/unprepare functions generic
  coresight: tmc: splitting driver in ETB/ETF and ETR components
  coresight: tmc: cleaning up header file
  ...
parents 19e36ad2 725d0123

Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10

+62 −7
Original line number Original line Diff line number Diff line
@@ -6,13 +6,6 @@ Description: (RW) Add/remove a sink from a trace path. There can be multiple 
		source for a single sink.

		source for a single sink.

		ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink

		ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink





What:		/sys/bus/coresight/devices/<memory_map>.etb/status

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) List various control and status registers.  The specific

		layout and content is driver specific.



What:		/sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr

What:		/sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr

Date:		November 2014

Date:		November 2014

KernelVersion:	3.19

KernelVersion:	3.19
@@ -22,3 +15,65 @@ Description: (RW) Disables write access to the Trace RAM by stopping the 
		following the trigger event. The number of 32-bit words written

		following the trigger event. The number of 32-bit words written

		into the Trace RAM following the trigger event is equal to the

		into the Trace RAM following the trigger event is equal to the

		value stored in this register+1 (from ARM ETB-TRM).

		value stored in this register+1 (from ARM ETB-TRM).



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Defines the depth, in words, of the trace RAM in powers of

		2.  The value is read directly from HW register RDP, 0x004.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the ETB status register.  The value

		is read directly from HW register STS, 0x00C.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the ETB RAM Read Pointer register

		that is used to read entries from the Trace RAM over the APB

		interface.  The value is read directly from HW register RRP,

		0x014.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the ETB RAM Write Pointer register

		that is used to sets the write pointer to write entries from

		the CoreSight bus into the Trace RAM. The value is read directly

		from HW register RWP, 0x018.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Similar to "trigger_cntr" above except that this value is

		read directly from HW register TRG, 0x01C.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the ETB Control register. The value

		is read directly from HW register CTL, 0x020.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the ETB Formatter and Flush Status

		register.  The value is read directly from HW register FFSR,

		0x300.



What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the ETB Formatter and Flush Control

		register.  The value is read directly from HW register FFCR,

		0x304.

Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

+13 −0
Original line number Original line Diff line number Diff line
@@ -359,6 +359,19 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 
Description:	(R) Print the content of the Peripheral ID3 Register

Description:	(R) Print the content of the Peripheral ID3 Register

		(0xFEC).  The value is taken directly from the HW.

		(0xFEC).  The value is taken directly from the HW.





What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig

Date:		February 2016

KernelVersion:	4.07

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the trace configuration register

		(0x010) as currently set by SW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid

Date:		February 2016

KernelVersion:	4.07

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the trace ID register (0x040).



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0

Date:		April 2015

Date:		April 2015

KernelVersion:	4.01

KernelVersion:	4.01

Documentation/ABI/testing/sysfs-bus-coresight-devices-stm

0 → 100644
+53 −0
Original line number Original line Diff line number Diff line 
What:		/sys/bus/coresight/devices/<memory_map>.stm/enable_source

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Enable/disable tracing on this specific trace macrocell.

		Enabling the trace macrocell implies it has been configured

		properly and a sink has been identified for it.  The path

		of coresight components linking the source to the sink is

		configured and managed automatically by the coresight framework.



What:		/sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Provides access to the HW event enable register, used in

		conjunction with HW event bank select register.



What:		/sys/bus/coresight/devices/<memory_map>.stm/hwevent_select

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Gives access to the HW event block select register

		(STMHEBSR) in order to configure up to 256 channels.  Used in

		conjunction with "hwevent_enable" register as described above.



What:		/sys/bus/coresight/devices/<memory_map>.stm/port_enable

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Provides access to the stimulus port enable register

		(STMSPER).  Used in conjunction with "port_select" described

		below.



What:		/sys/bus/coresight/devices/<memory_map>.stm/port_select

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Used to determine which bank of stimulus port bit in

		register STMSPER (see above) apply to.



What:		/sys/bus/coresight/devices/<memory_map>.stm/status

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) List various control and status registers.  The specific

		layout and content is driver specific.



What:		/sys/bus/coresight/devices/<memory_map>.stm/traceid

Date:		April 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Holds the trace ID that will appear in the trace stream

		coming from this trace entity.

Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc

+77 −0
Original line number Original line Diff line number Diff line
@@ -6,3 +6,80 @@ Description: (RW) Disables write access to the Trace RAM by stopping the 
		formatter after a defined number of words have been stored

		formatter after a defined number of words have been stored

		following the trigger event. Additional interface for this

		following the trigger event. Additional interface for this

		driver are expected to be added as it matures.

		driver are expected to be added as it matures.



What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz

Date:           March 2016

KernelVersion:  4.7

Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>

Description:    (R) Defines the size, in 32-bit words, of the local RAM buffer.

                The value is read directly from HW register RSZ, 0x004.



What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts

Date:           March 2016

KernelVersion:  4.7

Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC status register.  The value

                is read directly from HW register STS, 0x00C.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC RAM Read Pointer register

		that is used to read entries from the Trace RAM over the APB

		interface.  The value is read directly from HW register RRP,

		0x014.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC RAM Write Pointer register

		that is used to sets the write pointer to write entries from

		the CoreSight bus into the Trace RAM. The value is read directly

		from HW register RWP, 0x018.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Similar to "trigger_cntr" above except that this value is

		read directly from HW register TRG, 0x01C.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC Control register. The value

		is read directly from HW register CTL, 0x020.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC Formatter and Flush Status

		register.  The value is read directly from HW register FFSR,

		0x300.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC Formatter and Flush Control

		register.  The value is read directly from HW register FFCR,

		0x304.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Shows the value held by the TMC Mode register, which

		indicate the mode the device has been configured to enact.  The

		The value is read directly from the MODE register, 0x028.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid

Date:		March 2016

KernelVersion:	4.7

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the capabilities of the Coresight TMC.

		The value is read directly from the DEVID register, 0xFC8,

Documentation/ABI/testing/sysfs-bus-mcb

0 → 100644
+29 −0
Original line number Original line Diff line number Diff line 
What:		/sys/bus/mcb/devices/mcb:X

Date:		March 2016

KernelVersion:	4.7

Contact:	Johannes Thumshirn <jth@kernel.org>

Description:	Hardware chip or device hosting the MEN chameleon bus



What:		/sys/bus/mcb/devices/mcb:X/revision

Date:		March 2016

KernelVersion:	4.7

Contact:	Johannes Thumshirn <jth@kernel.org>

Description:	The FPGA's revision number



What:		/sys/bus/mcb/devices/mcb:X/minor

Date:		March 2016

KernelVersion:	4.7

Contact:	Johannes Thumshirn <jth@kernel.org>

Description:	The FPGA's minor number



What:		/sys/bus/mcb/devices/mcb:X/model

Date:		March 2016

KernelVersion:	4.7

Contact:	Johannes Thumshirn <jth@kernel.org>

Description:	The FPGA's model number



What:		/sys/bus/mcb/devices/mcb:X/name

Date:		March 2016

KernelVersion:	4.7

Contact:	Johannes Thumshirn <jth@kernel.org>

Description:	The FPGA's name