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Commit 5924ad0d authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Update SH-X3 subtype for clkdev lookups. 



Rewrite the SH-X3 proto CPU clock framework for clkdev.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 68a1aed7

arch/sh/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -570,7 +570,7 @@ config SH_CLK_CPG 
config SH_CLK_CPG_LEGACY

	depends on SH_CLK_CPG

	def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \

		      !CPU_SUBTYPE_SH7786 && !CPU_SUBTYPE_SH7757

		      !CPU_SHX3 && !CPU_SUBTYPE_SH7757



config SH_CLK_MD

	int "CPU Mode Pin Setting"

arch/sh/include/cpu-sh4/cpu/freq.h

+3 −1
Original line number Diff line number Diff line
@@ -56,7 +56,9 @@ 
#define FRQCR1			0xffc40004

#define FRQMR1			0xffc40014

#elif defined(CONFIG_CPU_SUBTYPE_SHX3)

#define FRQCR			0xffc00014

#define FRQCR0			0xffc00000

#define FRQCR1			0xffc00004

#define FRQMR1			0xffc00014

#else

#define FRQCR			0xffc00000

#define FRQCR_PSTBY		0x0200

arch/sh/kernel/cpu/sh4a/clock-shx3.c

+142 −83
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
 *

 *  Copyright (C) 2006-2007  Renesas Technology Corp.

 *  Copyright (C) 2006-2007  Renesas Solutions Corp.

 *  Copyright (C) 2006-2007  Paul Mundt

 *  Copyright (C) 2006-2010  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive
@@ -18,120 +18,179 @@ 
#include <asm/clock.h>

#include <asm/freq.h>



static int ifc_divisors[] = { 1, 2, 4 ,6 };

static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };

static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };

static int cfc_divisors[] = { 1, 1, 4, 6 };



#define IFC_POS		28

#define IFC_MSK		0x0003

#define BFC_MSK		0x000f

#define PFC_MSK		0x000f

#define CFC_MSK		0x0003

#define BFC_POS		16

#define PFC_POS		0

#define CFC_POS		20



static void master_clk_init(struct clk *clk)

{

	clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];

}



static struct clk_ops shx3_master_clk_ops = {

	.init		= master_clk_init,

/*

 * Default rate for the root input clock, reset this with clk_set_rate()

 * from the platform code.

 */

static struct clk extal_clk = {

	.rate		= 16666666,

};



static unsigned long module_clk_recalc(struct clk *clk)

static unsigned long pll_recalc(struct clk *clk)

{

	int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);

	return clk->parent->rate / pfc_divisors[idx];

	/* PLL1 has a fixed x72 multiplier.  */

	return clk->parent->rate * 72;

}



static struct clk_ops shx3_module_clk_ops = {

	.recalc		= module_clk_recalc,

static struct clk_ops pll_clk_ops = {

	.recalc		= pll_recalc,

};



static unsigned long bus_clk_recalc(struct clk *clk)

{

	int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);

	return clk->parent->rate / bfc_divisors[idx];

}

static struct clk pll_clk = {

	.ops		= &pll_clk_ops,

	.parent		= &extal_clk,

	.flags		= CLK_ENABLE_ON_INIT,

};



static struct clk_ops shx3_bus_clk_ops = {

	.recalc		= bus_clk_recalc,

static struct clk *clks[] = {

	&extal_clk,

	&pll_clk,

};



static unsigned long cpu_clk_recalc(struct clk *clk)

{

	int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);

	return clk->parent->rate / ifc_divisors[idx];

}

static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,

			       24, 32, 36, 48 };



static struct clk_ops shx3_cpu_clk_ops = {

	.recalc		= cpu_clk_recalc,

static struct clk_div_mult_table div4_div_mult_table = {

	.divisors = div2,

	.nr_divisors = ARRAY_SIZE(div2),

};



static struct clk_ops *shx3_clk_ops[] = {

	&shx3_master_clk_ops,

	&shx3_module_clk_ops,

	&shx3_bus_clk_ops,

	&shx3_cpu_clk_ops,

static struct clk_div4_table div4_table = {

	.div_mult_table = &div4_div_mult_table,

};



void __init arch_init_clk_ops(struct clk_ops **ops, int idx)

{

	if (idx < ARRAY_SIZE(shx3_clk_ops))

		*ops = shx3_clk_ops[idx];

}



static unsigned long shyway_clk_recalc(struct clk *clk)

{

	int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);

	return clk->parent->rate / cfc_divisors[idx];

}

enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };



static struct clk_ops shx3_shyway_clk_ops = {

	.recalc		= shyway_clk_recalc,

};

#define DIV4(_bit, _mask, _flags) \

  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)



static struct clk shx3_shyway_clk = {

	.flags		= CLK_ENABLE_ON_INIT,

	.ops		= &shx3_shyway_clk_ops,

struct clk div4_clks[DIV4_NR] = {

	[DIV4_P] = DIV4(0, 0x0f80, 0),

	[DIV4_SHA] = DIV4(4, 0x0ff0, 0),

	[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),

	[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),

};



/*

 * Additional SHx3-specific on-chip clocks that aren't already part of the

 * clock framework

 */

static struct clk *shx3_onchip_clocks[] = {

	&shx3_shyway_clk,

#define MSTPCR0		0xffc00030

#define MSTPCR1		0xffc00034



enum { MSTP027, MSTP026, MSTP025, MSTP024,

       MSTP009, MSTP008, MSTP003, MSTP002,

       MSTP001, MSTP000, MSTP119, MSTP105,

       MSTP104, MSTP_NR };



static struct clk mstp_clks[MSTP_NR] = {

	/* MSTPCR0 */

	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),

	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),

	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),

	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),

	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

	[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),

	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

	[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

	[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),



	/* MSTPCR1 */

	[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),

	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),

	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),

};



#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }



static struct clk_lookup lookups[] = {

	/* main clocks */

	CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),

	CLKDEV_CON_ID("extal", &extal_clk),

	CLKDEV_CON_ID("pll_clk", &pll_clk),



	/* DIV4 clocks */

	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),

	CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),

	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),

	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),

	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),



	/* MSTP32 clocks */

	{

		/* SCIF3 */

		.dev_id		= "sh-sci.3",

		.con_id		= "sci_fck",

		.clk		= &mstp_clks[MSTP027],

	}, {

		/* SCIF2 */

		.dev_id		= "sh-sci.2",

		.con_id		= "sci_fck",

		.clk		= &mstp_clks[MSTP026],

	}, {

		/* SCIF1 */

		.dev_id		= "sh-sci.1",

		.con_id		= "sci_fck",

		.clk		= &mstp_clks[MSTP025],

	}, {

		/* SCIF0 */

		.dev_id		= "sh-sci.0",

		.con_id		= "sci_fck",

		.clk		= &mstp_clks[MSTP024],

	},

	CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),

	CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),

	CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),

	CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),

	{

		/* TMU0 */

		.dev_id		= "sh_tmu.0",

		.con_id		= "tmu_fck",

		.clk		= &mstp_clks[MSTP008],

	}, {

		/* TMU1 */

		.dev_id		= "sh_tmu.1",

		.con_id		= "tmu_fck",

		.clk		= &mstp_clks[MSTP008],

	}, {

		/* TMU2 */

		.dev_id		= "sh_tmu.2",

		.con_id		= "tmu_fck",

		.clk		= &mstp_clks[MSTP008],

	}, {

		/* TMU3 */

		.dev_id		= "sh_tmu.3",

		.con_id		= "tmu_fck",

		.clk		= &mstp_clks[MSTP009],

	}, {

		/* TMU4 */

		.dev_id		= "sh_tmu.4",

		.con_id		= "tmu_fck",

		.clk		= &mstp_clks[MSTP009],

	}, {

		/* TMU5 */

		.dev_id		= "sh_tmu.5",

		.con_id		= "tmu_fck",

		.clk		= &mstp_clks[MSTP009],

	},

	CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),

	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),

	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),

};



int __init arch_clk_init(void)

{

	struct clk *clk;

	int i, ret = 0;



	cpg_clk_init();



	clk = clk_get(NULL, "master_clk");

	for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {

		struct clk *clkp = shx3_onchip_clocks[i];



		clkp->parent = clk;

		ret |= clk_register(clkp);

	}



	clk_put(clk);

	for (i = 0; i < ARRAY_SIZE(clks); i++)

		ret |= clk_register(clks[i]);

	for (i = 0; i < ARRAY_SIZE(lookups); i++)

		clkdev_add(&lookups[i]);



	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)

		ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),

					   &div4_table);

	if (!ret)

		ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);



	return ret;

}