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Commit 570e2a74 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Clear TX FIFO reset master override bits on chv 



Clear the override bits to make sure the hardware manages
the TX FIFO reset master on its own.

v2: Squash with the earlier attempt at forcing the override bits

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a02ef3c7

drivers/gpu/drm/i915/i915_reg.h

+12 −0
Original line number Diff line number Diff line
@@ -796,6 +796,8 @@ enum punit_power_well { 
#define _VLV_PCS_DW0_CH1		0x8400

#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)

#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)

#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)

#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)

#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)



#define _VLV_PCS01_DW0_CH0		0x200
@@ -872,8 +874,18 @@ enum punit_power_well { 


#define _VLV_PCS_DW11_CH0		0x822c

#define _VLV_PCS_DW11_CH1		0x842c

#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)

#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)

#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)

#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)



#define _VLV_PCS01_DW11_CH0		0x022c

#define _VLV_PCS23_DW11_CH0		0x042c

#define _VLV_PCS01_DW11_CH1		0x262c

#define _VLV_PCS23_DW11_CH1		0x282c

#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)

#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)



#define _VLV_PCS_DW12_CH0		0x8230

#define _VLV_PCS_DW12_CH1		0x8430

#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)

drivers/gpu/drm/i915/intel_dp.c

+9 −0
Original line number Diff line number Diff line
@@ -2731,6 +2731,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) 


	mutex_lock(&dev_priv->dpio_lock);



	/* allow hardware to manage TX FIFO reset source */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);



	/* Deassert soft data lane reset*/

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

	val |= CHV_PCS_REQ_SOFTRESET_EN;

drivers/gpu/drm/i915/intel_hdmi.c

+9 −0
Original line number Diff line number Diff line
@@ -1400,6 +1400,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 


	mutex_lock(&dev_priv->dpio_lock);



	/* allow hardware to manage TX FIFO reset source */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);



	/* Deassert soft data lane reset*/

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

	val |= CHV_PCS_REQ_SOFTRESET_EN;