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Commit 54db01a2 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bna-cleanups' 



Ivan Vecera says:

====================
bna: clean-up 2

Next round of cleaning patches.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a2bb6d7d ebb56d37

drivers/net/ethernet/brocade/bna/bfa_defs_mfg_comm.h

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ do { \ 
		(prop) |= BFI_ADAPTER_PROTO;			\

		(gpio) &= ~CB_GPIO_PROTO;			\

	}							\

	switch ((gpio)) {					\

	switch (gpio) {						\

	case CB_GPIO_TTV:					\

		(prop) |= BFI_ADAPTER_TTV;			\

	case CB_GPIO_DFLY:					\

drivers/net/ethernet/brocade/bna/bfa_ioc.c

+5 −5
Original line number Diff line number Diff line
@@ -1304,7 +1304,7 @@ bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr) 
	for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));

	     i++) {

		fwsig[i] =

			swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));

			swab32(readl(loff + ioc->ioc_regs.smem_page_start));

		loff += sizeof(u32);

	}

}
@@ -1675,7 +1675,7 @@ bfa_raw_sem_get(void __iomem *bar) 
{

	int	locked;



	locked = readl((bar + FLASH_SEM_LOCK_REG));

	locked = readl(bar + FLASH_SEM_LOCK_REG);



	return !locked;

}
@@ -2049,8 +2049,8 @@ bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type, 
		/**

		 * write smem

		 */

		writel((swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)])),

			      ((ioc->ioc_regs.smem_page_start) + (loff)));

		writel(swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]),

		       ioc->ioc_regs.smem_page_start + loff);



		loff += sizeof(u32);
@@ -2213,7 +2213,7 @@ bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz) 


	len = sz/sizeof(u32);

	for (i = 0; i < len; i++) {

		r32 = swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));

		r32 = swab32(readl(loff + ioc->ioc_regs.smem_page_start));

		buf[i] = be32_to_cpu(r32);

		loff += sizeof(u32);

drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c

+50 −51
Original line number Diff line number Diff line
@@ -23,8 +23,7 @@ 
#include "bfi_reg.h"

#include "bfa_defs.h"



#define bfa_ioc_ct_sync_pos(__ioc)	\

		((u32)BIT(bfa_ioc_pcifn(__ioc)))

#define bfa_ioc_ct_sync_pos(__ioc)	BIT(bfa_ioc_pcifn(__ioc))

#define BFA_IOC_SYNC_REQD_SH		16

#define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)

#define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
@@ -536,7 +535,7 @@ bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc) 
{

	u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);



	writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);

	writel(r32 | bfa_ioc_ct_sync_pos(ioc), ioc->ioc_regs.ioc_fail_sync);

}



static bool
@@ -667,7 +666,7 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) 
		writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));

		writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));

	}

	r32 = readl((rb + PSS_CTL_REG));

	r32 = readl(rb + PSS_CTL_REG);

	r32 &= ~__PSS_LMEM_RESET;

	writel(r32, (rb + PSS_CTL_REG));

	udelay(1000);
@@ -678,7 +677,7 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) 


	writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));

	udelay(1000);

	r32 = readl((rb + MBIST_STAT_REG));

	r32 = readl(rb + MBIST_STAT_REG);

	writel(0, (rb + MBIST_CTL_REG));

	return BFA_STATUS_OK;

}
@@ -691,7 +690,7 @@ bfa_ioc_ct2_sclk_init(void __iomem *rb) 
	/*

	 * put s_clk PLL and PLL FSM in reset

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

	r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);

	r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |

		__APP_PLL_SCLK_LOGIC_SOFT_RESET);
@@ -701,28 +700,28 @@ bfa_ioc_ct2_sclk_init(void __iomem *rb) 
	 * Ignore mode and program for the max clock (which is FC16)

	 * Firmware/NFC will do the PLL init appropriately

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

	r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);

	writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * while doing PLL init dont clock gate ethernet subsystem

	 */

	r32 = readl((rb + CT2_CHIP_MISC_PRG));

	writel((r32 | __ETH_CLK_ENABLE_PORT0),

				(rb + CT2_CHIP_MISC_PRG));

	r32 = readl(rb + CT2_CHIP_MISC_PRG);

	writel(r32 | __ETH_CLK_ENABLE_PORT0,

	       rb + CT2_CHIP_MISC_PRG);



	r32 = readl((rb + CT2_PCIE_MISC_REG));

	writel((r32 | __ETH_CLK_ENABLE_PORT1),

				(rb + CT2_PCIE_MISC_REG));

	r32 = readl(rb + CT2_PCIE_MISC_REG);

	writel(r32 | __ETH_CLK_ENABLE_PORT1,

	       rb + CT2_PCIE_MISC_REG);



	/*

	 * set sclk value

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

	r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |

		__APP_PLL_SCLK_CLK_DIV2);

	writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));

	writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG);



	/*

	 * poll for s_clk lock or delay 1ms
@@ -743,28 +742,28 @@ bfa_ioc_ct2_lclk_init(void __iomem *rb) 
	/*

	 * put l_clk PLL and PLL FSM in reset

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

	r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);

	r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |

		__APP_PLL_LCLK_LOGIC_SOFT_RESET);

	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);



	/*

	 * set LPU speed (set for FC16 which will work for other modes)

	 */

	r32 = readl((rb + CT2_CHIP_MISC_PRG));

	r32 = readl(rb + CT2_CHIP_MISC_PRG);

	writel(r32, (rb + CT2_CHIP_MISC_PRG));



	/*

	 * set LPU half speed (set for FC16 which will work for other modes)

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

	writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);



	/*

	 * set lclk for mode (set for FC16)

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

	r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);

	r32 |= 0x20c1731b;

	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
@@ -780,14 +779,14 @@ bfa_ioc_ct2_mem_init(void __iomem *rb) 
{

	u32 r32;



	r32 = readl((rb + PSS_CTL_REG));

	r32 = readl(rb + PSS_CTL_REG);

	r32 &= ~__PSS_LMEM_RESET;

	writel(r32, (rb + PSS_CTL_REG));

	writel(r32, rb + PSS_CTL_REG);

	udelay(1000);



	writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));

	writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG);

	udelay(1000);

	writel(0, (rb + CT2_MBIST_CTL_REG));

	writel(0, rb + CT2_MBIST_CTL_REG);

}



static void
@@ -801,22 +800,22 @@ bfa_ioc_ct2_mac_reset(void __iomem *rb) 
	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	writel((r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET),

			(rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

	writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,

	       rb + CT2_APP_PLL_SCLK_CTL_REG);



	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET),

			(rb + CT2_APP_PLL_LCLK_CTL_REG));

	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

	writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,

	       rb + CT2_APP_PLL_LCLK_CTL_REG);



	/* put port0, port1 MAC & AHB in reset */

	writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),

			(rb + CT2_CSI_MAC_CONTROL_REG(0)));

	writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),

			(rb + CT2_CSI_MAC_CONTROL_REG(1)));

	writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET,

	       rb + CT2_CSI_MAC_CONTROL_REG(0));

	writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET,

	       rb + CT2_CSI_MAC_CONTROL_REG(1));

}



#define CT2_NFC_MAX_DELAY       1000
@@ -861,8 +860,8 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) 


	nfc_ver = readl(rb + CT2_RSC_GPR15_REG);



	if ((wgn == (__A2T_AHB_LOAD | __WGN_READY)) &&

		(nfc_ver >= CT2_NFC_VER_VALID)) {

	if (wgn == (__A2T_AHB_LOAD | __WGN_READY) &&

	    nfc_ver >= CT2_NFC_VER_VALID) {

		if (bfa_ioc_ct2_nfc_halted(rb))

			bfa_ioc_ct2_nfc_resume(rb);

		writel(__RESET_AND_START_SCLK_LCLK_PLLS,
@@ -899,19 +898,19 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) 
		bfa_ioc_ct2_lclk_init(rb);



		/* release soft reset on s_clk & l_clk */

		r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

		r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

		writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,

				rb + CT2_APP_PLL_SCLK_CTL_REG);

		r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

		r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

		writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,

				rb + CT2_APP_PLL_LCLK_CTL_REG);

	}



	/* Announce flash device presence, if flash was corrupted. */

	if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {

		r32 = readl((rb + PSS_GPIO_OUT_REG));

		r32 = readl(rb + PSS_GPIO_OUT_REG);

		writel(r32 & ~1, rb + PSS_GPIO_OUT_REG);

		r32 = readl((rb + PSS_GPIO_OE_REG));

		r32 = readl(rb + PSS_GPIO_OE_REG);

		writel(r32 | 1, rb + PSS_GPIO_OE_REG);

	}
@@ -919,27 +918,27 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) 
	 * Mask the interrupts and clear any

	 * pending interrupts left by BIOS/EFI

	 */

	writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));

	writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));

	writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK);

	writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK);



	/* For first time initialization, no need to clear interrupts */

	r32 = readl(rb + HOST_SEM5_REG);

	if (r32 & 0x1) {

		r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

		r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);

		if (r32 == 1) {

			writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));

			readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

			writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT);

			readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);

		}

		r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

		r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);

		if (r32 == 1) {

			writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));

			readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

			writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT);

			readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);

		}

	}



	bfa_ioc_ct2_mem_init(rb);



	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));

	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));

	writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG);

	writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG);

	return BFA_STATUS_OK;

}

drivers/net/ethernet/brocade/bna/bna.h

+9 −10
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ do { \ 


/*  Inline functions  */



static inline struct bna_mac *bna_mac_find(struct list_head *q, u8 *addr)

static inline struct bna_mac *bna_mac_find(struct list_head *q, const u8 *addr)

{

	struct bna_mac *mac;
@@ -362,15 +362,14 @@ void bna_rx_cleanup_complete(struct bna_rx *rx); 
void bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo);

void bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX]);

void bna_rx_dim_update(struct bna_ccb *ccb);

enum bna_cb_status

bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac);

enum bna_cb_status

bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist);

enum bna_cb_status

bna_rx_mcast_add(struct bna_rx *rx, u8 *mcmac,

		 void (*cbfn)(struct bnad *, struct bna_rx *));

enum bna_cb_status

bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mcmac);

enum bna_cb_status bna_rx_ucast_set(struct bna_rx *rx, const u8 *ucmac);

enum bna_cb_status bna_rx_ucast_listset(struct bna_rx *rx, int count,

					const u8 *uclist);

enum bna_cb_status bna_rx_mcast_add(struct bna_rx *rx, const u8 *mcmac,

				    void (*cbfn)(struct bnad *,

						 struct bna_rx *));

enum bna_cb_status bna_rx_mcast_listset(struct bna_rx *rx, int count,

					const u8 *mcmac);

void

bna_rx_mcast_delall(struct bna_rx *rx);

enum bna_cb_status

drivers/net/ethernet/brocade/bna/bna_enet.c

+2 −2
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ bna_bfi_stats_get_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr) 
	for (i = 0; i < BFI_ENET_CFG_MAX; i++) {

		stats_dst = (u64 *)&(bna->stats.hw_stats.rxf_stats[i]);

		memset(stats_dst, 0, sizeof(struct bfi_enet_stats_rxf));

		if (rx_enet_mask & ((u32)BIT(i))) {

		if (rx_enet_mask & BIT(i)) {

			int k;

			count = sizeof(struct bfi_enet_stats_rxf) /

				sizeof(u64);
@@ -222,7 +222,7 @@ bna_bfi_stats_get_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr) 
	for (i = 0; i < BFI_ENET_CFG_MAX; i++) {

		stats_dst = (u64 *)&(bna->stats.hw_stats.txf_stats[i]);

		memset(stats_dst, 0, sizeof(struct bfi_enet_stats_txf));

		if (tx_enet_mask & ((u32)BIT(i))) {

		if (tx_enet_mask & BIT(i)) {

			int k;

			count = sizeof(struct bfi_enet_stats_txf) /

				sizeof(u64);