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Commit 529c4b05 authored by Kristina Martsenko's avatar Kristina Martsenko Committed by Catalin Marinas
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arm64: handle 52-bit addresses in TTBR 



The top 4 bits of a 52-bit physical address are positioned at bits 2..5
in the TTBR registers. Introduce a couple of macros to move the bits
there, and change all TTBR writers to use them.

Leave TTBR0 PAN code unchanged, to avoid complicating it. A system with
52-bit PA will have PAN anyway (because it's ARMv8.1 or later), and a
system without 52-bit PA can only use up to 48-bit PAs. A later patch in
this series will add a kconfig dependency to ensure PAN is configured.

In addition, when using 52-bit PA there is a special alignment
requirement on the top-level table. We don't currently have any VA_BITS
configuration that would violate the requirement, but one could be added
in the future, so add a compile-time BUG_ON to check for it.

Tested-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Tested-by: default avatarBob Picco <bob.picco@oracle.com>
Reviewed-by: default avatarBob Picco <bob.picco@oracle.com>
Signed-off-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
[catalin.marinas@arm.com: added TTBR_BADD_MASK_52 comment]
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 787fd1d0

arch/arm/include/asm/kvm_mmu.h

+2 −0
Original line number Diff line number Diff line
@@ -221,6 +221,8 @@ static inline unsigned int kvm_get_vmid_bits(void) 
	return 8;

}



#define kvm_phys_to_vttbr(addr)		(addr)



#endif	/* !__ASSEMBLY__ */



#endif /* __ARM_KVM_MMU_H__ */

arch/arm64/include/asm/assembler.h

+16 −0
Original line number Diff line number Diff line
@@ -530,4 +530,20 @@ alternative_else_nop_endif 
#endif

	.endm



/*

 * Arrange a physical address in a TTBR register, taking care of 52-bit

 * addresses.

 *

 * 	phys:	physical address, preserved

 * 	ttbr:	returns the TTBR value

 */

	.macro	phys_to_ttbr, phys, ttbr

#ifdef CONFIG_ARM64_PA_BITS_52

	orr	\ttbr, \phys, \phys, lsr #46

	and	\ttbr, \ttbr, #TTBR_BADDR_MASK_52

#else

	mov	\ttbr, \phys

#endif

	.endm



#endif	/* __ASM_ASSEMBLER_H */

arch/arm64/include/asm/kvm_mmu.h

+2 −0
Original line number Diff line number Diff line
@@ -309,5 +309,7 @@ static inline unsigned int kvm_get_vmid_bits(void) 
	return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;

}



#define kvm_phys_to_vttbr(addr)		phys_to_ttbr(addr)



#endif /* __ASSEMBLY__ */

#endif /* __ARM64_KVM_MMU_H__ */

arch/arm64/include/asm/mmu_context.h

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static inline void contextidr_thread_switch(struct task_struct *next) 
 */

static inline void cpu_set_reserved_ttbr0(void)

{

	unsigned long ttbr = __pa_symbol(empty_zero_page);

	unsigned long ttbr = phys_to_ttbr(__pa_symbol(empty_zero_page));



	write_sysreg(ttbr, ttbr0_el1);

	isb();

arch/arm64/include/asm/pgtable-hwdef.h

+13 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
#ifndef __ASM_PGTABLE_HWDEF_H

#define __ASM_PGTABLE_HWDEF_H



#include <asm/memory.h>



/*

 * Number of page-table levels required to address 'va_bits' wide

 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
@@ -279,4 +281,15 @@ 
#define TCR_HA			(UL(1) << 39)

#define TCR_HD			(UL(1) << 40)



/*

 * TTBR.

 */

#ifdef CONFIG_ARM64_PA_BITS_52

/*

 * This should be GENMASK_ULL(47, 2).

 * TTBR_ELx[1] is RES0 in this configuration.

 */

#define TTBR_BADDR_MASK_52	(((UL(1) << 46) - 1) << 2)

#endif



#endif