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Commit 51aa68e7 authored by Jim Mattson's avatar Jim Mattson Committed by Paolo Bonzini
Browse files

kvm: nVMX: Don't allow L2 to access the hardware CR8 



If L1 does not specify the "use TPR shadow" VM-execution control in
vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
exiting" VM-execution controls in vmcs02. Failure to do so will give
the L2 VM unrestricted read/write access to the hardware CR8.

This fixes CVE-2017-12154.

Signed-off-by: default avatarJim Mattson <jmattson@google.com>
Reviewed-by: default avatarDavid Hildenbrand <david@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 488e32f1

arch/x86/kvm/vmx.c

+5 −0
Original line number Diff line number Diff line
@@ -10525,6 +10525,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 
	if (exec_control & CPU_BASED_TPR_SHADOW) {

		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);

		vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);

	} else {

#ifdef CONFIG_X86_64

		exec_control |= CPU_BASED_CR8_LOAD_EXITING |

				CPU_BASED_CR8_STORE_EXITING;

#endif

	}



	/*