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Commit 4715c14b authored by James Morse's avatar James Morse Committed by Catalin Marinas
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KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2. 



Prior to v8.2's RAS Extensions, the HCR_EL2.VSE 'virtual SError' feature
generated an SError with an implementation defined ESR_EL1.ISS, because we
had no mechanism to specify the ESR value.

On Juno this generates an all-zero ESR, the most significant bit 'ISV'
is clear indicating the remainder of the ISS field is invalid.

With the RAS Extensions we have a mechanism to specify this value, and the
most significant bit has a new meaning: 'IDS - Implementation Defined
Syndrome'. An all-zero SError ESR now means: 'RAS error: Uncategorized'
instead of 'no valid ISS'.

Add KVM support for the VSESR_EL2 register to specify an ESR value when
HCR_EL2.VSE generates a virtual SError. Change kvm_inject_vabt() to
specify an implementation-defined value.

We only need to restore the VSESR_EL2 value when HCR_EL2.VSE is set, KVM
save/restores this bit during __{,de}activate_traps() and hardware clears the
bit once the guest has consumed the virtual-SError.

Future patches may add an API (or KVM CAP) to pend a virtual SError with
a specified ESR.

Cc: Dongjiu Geng <gengdongjiu@huawei.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 4f5abad9

arch/arm64/include/asm/kvm_emulate.h

+5 −0
Original line number Diff line number Diff line
@@ -64,6 +64,11 @@ static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr) 
	vcpu->arch.hcr_el2 = hcr;

}



static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)

{

	vcpu->arch.vsesr_el2 = vsesr;

}



static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)

{

	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;

arch/arm64/include/asm/kvm_host.h

+3 −0
Original line number Diff line number Diff line
@@ -280,6 +280,9 @@ struct kvm_vcpu_arch { 


	/* Detect first run of a vcpu */

	bool has_run_once;



	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */

	u64 vsesr_el2;

};



#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -355,6 +355,7 @@ 


#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)

#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)

#define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)

#define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)



#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)

arch/arm64/kvm/hyp/switch.c

+3 −0
Original line number Diff line number Diff line
@@ -94,6 +94,9 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) 


	write_sysreg(val, hcr_el2);



	if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (val & HCR_VSE))

		write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);



	/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */

	write_sysreg(1 << 15, hstr_el2);

	/*

arch/arm64/kvm/inject_fault.c

+12 −1
Original line number Diff line number Diff line
@@ -164,14 +164,25 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu) 
		inject_undef64(vcpu);

}



static void pend_guest_serror(struct kvm_vcpu *vcpu, u64 esr)

{

	vcpu_set_vsesr(vcpu, esr);

	vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) | HCR_VSE);

}



/**

 * kvm_inject_vabt - inject an async abort / SError into the guest

 * @vcpu: The VCPU to receive the exception

 *

 * It is assumed that this code is called from the VCPU thread and that the

 * VCPU therefore is not currently executing guest code.

 *

 * Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with

 * the remaining ISS all-zeros so that this error is not interpreted as an

 * uncategorized RAS error. Without the RAS Extensions we can't specify an ESR

 * value, so the CPU generates an imp-def value.

 */

void kvm_inject_vabt(struct kvm_vcpu *vcpu)

{

	vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) | HCR_VSE);

	pend_guest_serror(vcpu, ESR_ELx_ISV);

}