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Commit 407a2c72 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The irq departement delivers:

   - plug a potential race related to chained interrupt handlers

   - core updates which address the needs of the x86 irqdomain conversion

   - new irqchip callback to support affinity settings for VCPUs

   - the usual pile of updates to interrupt chip drivers

   - a few helper functions to allow further cleanups and
     simplifications

  I have a largish pile of coccinelle scripted/verified cleanups and
  simplifications pending on top of that, but I prefer to send that
  towards the end of the merge window when the arch/driver changes have
  hit your tree to avoid API change wreckage as far as possible"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits)
  genirq: Remove bogus restriction in irq_move_mask_irq()
  irqchip: atmel-aic5: Add sama5d2 support
  irq: spear-shirq: Fix race in installing chained IRQ handler
  irq: irq-keystone: Fix race in installing chained IRQ handler
  gpio: gpio-tegra: Fix race in installing chained IRQ handler
  gpio: gpio-mxs: Fix race in installing chained IRQ handler
  gpio: gpio-mxc: Fix race in installing chained IRQ handler
  ARM: gemini: Fix race in installing GPIO chained IRQ handler
  GPU: ipu: Fix race in installing IPU chained IRQ handler
  ARM: sa1100: convert SA11x0 related code to use new chained handler helper
  irq: Add irq_set_chained_handler_and_data()
  irqchip: exynos-combiner: Save IRQ enable set on suspend
  genirq: Introduce helper function irq_data_get_affinity_mask()
  genirq: Introduce helper function irq_data_get_node()
  genirq: Introduce struct irq_common_data to host shared irq data
  genirq: Prevent crash in irq_move_irq()
  genirq: Enhance irq_data_to_desc() to support hierarchy irqdomain
  irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKED
  irqchip: renesas: intc-irqpin: Improve binding documentation
  genirq: Set IRQCHIP_SKIP_SET_WAKE for no_irq_chip
  ...
parents 3a95398f f0521865

Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 


Required properties:

- compatible: Should be "atmel,<chip>-aic"

  <chip> can be "at91rm9200", "sama5d3" or "sama5d4"

  <chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4"

- interrupt-controller: Identifies the node as an interrupt controller.

- interrupt-parent: For single AIC system, it is an empty property.

- #interrupt-cells: The number of cells to define the interrupts. It should be 3.

Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt

+37 −2
Original line number Diff line number Diff line
@@ -13,9 +13,12 @@ Required properties: 
- reg: Base address and length of each register bank used by the external

  IRQ pins driven by the interrupt controller hardware module. The base

  addresses, length and number of required register banks varies with soctype.



- interrupt-controller: Identifies the node as an interrupt controller.

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

  interrupts.txt in this directory.

- interrupts: Must contain a list of interrupt specifiers. For each interrupt

  provided by this irqpin controller instance, there must be one entry,

  referring to the corresponding parent interrupt.



Optional properties:
@@ -25,3 +28,35 @@ Optional properties: 
  if different from the default 4 bits

- control-parent: disable and enable interrupts on the parent interrupt

  controller, needed for some broken implementations

- clocks: Must contain a reference to the functional clock.  This property is

  mandatory if the hardware implements a controllable functional clock for

  the irqpin controller instance.

- power-domains: Must contain a reference to the power domain. This property is

  mandatory if the irqpin controller instance is part of a controllable power

  domain.





Example

-------



	irqpin1: interrupt-controller@e6900004 {

		compatible = "renesas,intc-irqpin-r8a7740",

			     "renesas,intc-irqpin";

		#interrupt-cells = <2>;

		interrupt-controller;

		reg = <0xe6900004 4>,

			<0xe6900014 4>,

			<0xe6900024 1>,

			<0xe6900044 1>,

			<0xe6900064 1>;

		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;

		power-domains = <&pd_a4s>;

	};

arch/arm/common/sa1111.c

+3 −4
Original line number Diff line number Diff line
@@ -501,8 +501,8 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) 
	 * Register SA1111 interrupt

	 */

	irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);

	irq_set_handler_data(sachip->irq, sachip);

	irq_set_chained_handler(sachip->irq, sa1111_irq_handler);

	irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,

					 sachip);



	dev_info(sachip->dev, "Providing IRQ%u-%u\n",

		sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
@@ -836,8 +836,7 @@ static void __sa1111_remove(struct sa1111 *sachip) 
	clk_unprepare(sachip->clk);



	if (sachip->irq != NO_IRQ) {

		irq_set_chained_handler(sachip->irq, NULL);

		irq_set_handler_data(sachip->irq, NULL);

		irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);

		irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);



		release_mem_region(sachip->phys + SA1111_INTC, 512);

arch/arm/mach-gemini/gpio.c

+2 −2
Original line number Diff line number Diff line
@@ -223,8 +223,8 @@ void __init gemini_gpio_init(void) 
			set_irq_flags(j, IRQF_VALID);

		}



		irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);

		irq_set_handler_data(IRQ_GPIO(i), (void *)i);

		irq_set_chained_handler_and_data(IRQ_GPIO(i), gpio_irq_handler,

						 (void *)i);

	}



	BUG_ON(gpiochip_add(&gemini_gpio_chip));

arch/arm/mach-sa1100/neponset.c

+1 −2
Original line number Diff line number Diff line
@@ -327,8 +327,7 @@ static int neponset_probe(struct platform_device *dev) 
	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);



	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);

	irq_set_handler_data(irq, d);

	irq_set_chained_handler(irq, neponset_irq_handler);

	irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);



	/*

	 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately