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Commit 3d90e649 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Protect cxsr state with wm_mutex 



Let's protect the cxsr state with the wm_mutex, since it might
get poked from multiple places if there's a parallel plane update
happening with a pipe getting enable/disabled.

It's still pretty racy for the old platforms, but for vlv/chv it
should work, I think. If not, we'll improve it later anyway.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-10-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent 7c951c00

drivers/gpu/drm/i915/intel_display.c

+0 −2
Original line number Diff line number Diff line
@@ -5023,7 +5023,6 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) 
	 */

	if (HAS_GMCH_DISPLAY(dev_priv)) {

		intel_set_memory_cxsr(dev_priv, false);

		dev_priv->wm.vlv.cxsr = false;

		intel_wait_for_vblank(dev_priv, pipe);

	}

}
@@ -5102,7 +5101,6 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) 
		 */

		if (old_crtc_state->base.active) {

			intel_set_memory_cxsr(dev_priv, false);

			dev_priv->wm.vlv.cxsr = false;

			intel_wait_for_vblank(dev_priv, crtc->pipe);

		}

	}

drivers/gpu/drm/i915/intel_pm.c

+10 −4
Original line number Diff line number Diff line
@@ -312,14 +312,13 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 
#define FW_WM(value, plane) \

	(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)



void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)

static void _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)

{

	u32 val;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);

		POSTING_READ(FW_BLC_SELF_VLV);

		dev_priv->wm.vlv.cxsr = enable;

	} else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {

		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

		POSTING_READ(FW_BLC_SELF);
@@ -350,6 +349,13 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 
	DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable));

}



void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)

{

	mutex_lock(&dev_priv->wm.wm_mutex);

	_intel_set_memory_cxsr(dev_priv, enable);

	dev_priv->wm.vlv.cxsr = enable;

	mutex_unlock(&dev_priv->wm.wm_mutex);

}



/*

 * Latency for FIFO fetches is dependent on several factors:
@@ -1322,7 +1328,7 @@ static void vlv_update_wm(struct intel_crtc *crtc) 
		chv_set_memory_pm5(dev_priv, false);



	if (!wm.cxsr && dev_priv->wm.vlv.cxsr)

		intel_set_memory_cxsr(dev_priv, false);

		_intel_set_memory_cxsr(dev_priv, false);



	/* FIXME should be part of crtc atomic commit */

	vlv_pipe_set_fifo_size(crtc);
@@ -1336,7 +1342,7 @@ static void vlv_update_wm(struct intel_crtc *crtc) 
		      wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);



	if (wm.cxsr && !dev_priv->wm.vlv.cxsr)

		intel_set_memory_cxsr(dev_priv, true);

		_intel_set_memory_cxsr(dev_priv, true);



	if (wm.level >= VLV_WM_LEVEL_PM5 &&

	    dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)