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Commit 38760d40 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] time: Replace plat_timer_setup with modern APIs. 



plat_timer_setup is no longer getting called.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1238d5d8

arch/mips/kernel/cevt-r4k.c

+18 −7
Original line number Diff line number Diff line
@@ -224,7 +224,7 @@ void __cpuinit mips_clockevent_init(void) 
	uint64_t mips_freq = mips_hpt_frequency;

	unsigned int cpu = smp_processor_id();

	struct clock_event_device *cd;

	unsigned int irq = MIPS_CPU_IRQ_BASE + 7;

	unsigned int irq;



	if (!cpu_has_counter || !mips_hpt_frequency)

		return;
@@ -243,6 +243,15 @@ void __cpuinit mips_clockevent_init(void) 
	if (!c0_compare_int_usable())

		return;



	/*

	 * With vectored interrupts things are getting platform specific.

	 * get_c0_compare_int is a hook to allow a platform to return the

	 * interrupt number of it's liking.

	 */

	irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;

	if (get_c0_compare_int)

		irq = get_c0_compare_int();



	cd = &per_cpu(mips_clockevent_device, cpu);



	cd->name		= "MIPS";
@@ -267,13 +276,15 @@ void __cpuinit mips_clockevent_init(void) 


	clockevents_register_device(cd);



	if (!cp0_timer_irq_installed) {

	if (!cp0_timer_irq_installed)

		return;



	cp0_timer_irq_installed = 1;



#ifdef CONFIG_MIPS_MT_SMTC

#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)

	setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);

#else

	setup_irq(irq, &c0_compare_irqaction);

#endif /* CONFIG_MIPS_MT_SMTC */

		cp0_timer_irq_installed = 1;

	}

#endif

}

arch/mips/mips-boards/generic/time.c

+22 −30
Original line number Diff line number Diff line
@@ -127,26 +127,6 @@ unsigned long read_persistent_clock(void) 
	return mc146818_get_cmos_time();

}



void __init plat_time_init(void)

{

	unsigned int est_freq;



        /* Set Data mode - binary. */

        CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);



	est_freq = estimate_cpu_frequency();



	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,

	       (est_freq%1000000)*100/1000000);



        cpu_khz = est_freq / 1000;



	mips_scroll_message();

#ifdef CONFIG_I8253		/* Only Malta has a PIT */

	setup_pit_timer();

#endif

}



void __init plat_perf_setup(void)

{

	cp0_perfcount_irq = -1;
@@ -166,14 +146,13 @@ void __init plat_perf_setup(void) 
	}

}



void __init plat_timer_setup(struct irqaction *irq)

unsigned int __init get_c0_compare_int(void)

{

#ifdef MSC01E_INT_BASE

	if (cpu_has_veic) {

		set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);

		mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;

	}

	else

	} else

#endif

	{

		if (cpu_has_vint)
@@ -181,13 +160,26 @@ void __init plat_timer_setup(struct irqaction *irq) 
		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;

	}



#ifdef CONFIG_MIPS_MT_SMTC

	setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);

#else

	setup_irq(mips_cpu_timer_irq, irq);

#endif /* CONFIG_MIPS_MT_SMTC */

#ifdef CONFIG_SMP

	set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);

	return mips_cpu_timer_irq;

}



void __init plat_time_init(void)

{

	unsigned int est_freq;



        /* Set Data mode - binary. */

        CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);



	est_freq = estimate_cpu_frequency();



	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,

	       (est_freq%1000000)*100/1000000);



        cpu_khz = est_freq / 1000;



	mips_scroll_message();

#ifdef CONFIG_I8253		/* Only Malta has a PIT */

	setup_pit_timer();

#endif



	plat_perf_setup();

arch/mips/mipssim/sim_time.c

+22 −30
Original line number Diff line number Diff line
@@ -75,25 +75,6 @@ static unsigned int __init estimate_cpu_frequency(void) 
	return count;

}



void __init plat_time_init(void)

{

	unsigned int est_freq, flags;



	local_irq_save(flags);



	/* Set Data mode - binary. */

	CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);



	est_freq = estimate_cpu_frequency();



	printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,

	       (est_freq % 1000000) * 100 / 1000000);



	cpu_khz = est_freq / 1000;



	local_irq_restore(flags);

}



static int mips_cpu_timer_irq;



static void mips_timer_dispatch(void)
@@ -102,26 +83,37 @@ static void mips_timer_dispatch(void) 
}





void __init plat_timer_setup(struct irqaction *irq)

unsigned __init get_c0_compare_int(void)

{

#ifdef MSC01E_INT_BASE

	if (cpu_has_veic) {

		set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);

		mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;

	} else {

#endif

		if (cpu_has_vint)

			set_vi_handler(cp0_compare_irq, mips_timer_dispatch);

		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;

	}



	/* we are using the cpu counter for timer interrupts */

	setup_irq(mips_cpu_timer_irq, irq);

	return mips_cpu_timer_irq;

}



#ifdef CONFIG_SMP

	/* irq_desc(riptor) is a global resource, when the interrupt overlaps

	   on seperate cpu's the first one tries to handle the second interrupt.

	   The effect is that the int remains disabled on the second cpu.

	   Mark the interrupt with IRQ_PER_CPU to avoid any confusion */

	irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;

	set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);

#endif

void __init plat_time_init(void)

{

	unsigned int est_freq, flags;



	local_irq_save(flags);



	/* Set Data mode - binary. */

	CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);



	est_freq = estimate_cpu_frequency();



	printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,

	       (est_freq % 1000000) * 100 / 1000000);



	cpu_khz = est_freq / 1000;



	local_irq_restore(flags);

}

include/asm-mips/time.h

+1 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ extern int (*perf_irq)(void); 
 */

#ifdef CONFIG_CEVT_R4K

extern void mips_clockevent_init(void);

extern unsigned int __weak get_c0_compare_int(void);

#else

static inline void mips_clockevent_init(void)

{