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Commit 3858f8f9 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt 

From Shawn Guo <shawn.guo@linaro.org>:

* 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6

:
  ARM: imx6q: add clocks for gpmi-nand
  ARM: imx: enable flexcan on imx25, imx35, imx53, imx6q
  ARM: imx6q: add DT node for gpmi nand
  ARM: imx6q: add clock for apbh-dma
  ARM: imx6q: add DT node for apbh-dma

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 059eab45 77ac32ad

arch/arm/boot/dts/imx6q-arm2.dts

+6 −0
Original line number Diff line number Diff line
@@ -22,6 +22,12 @@ 
	};



	soc {

		gpmi-nand@00112000 {

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_gpmi_nand_1>;

			status = "disabled"; /* gpmi nand conflicts with SD */

		};



		aips-bus@02100000 { /* AIPS2 */

			ethernet@02188000 {

				phy-mode = "rgmii";

arch/arm/boot/dts/imx6q.dtsi

+41 −0
Original line number Diff line number Diff line
@@ -87,6 +87,23 @@ 
		interrupt-parent = <&intc>;

		ranges;



		dma-apbh@00110000 {

			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";

			reg = <0x00110000 0x2000>;

		};



		gpmi-nand@00112000 {

		       compatible = "fsl,imx6q-gpmi-nand";

		       #address-cells = <1>;

		       #size-cells = <1>;

		       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;

		       reg-names = "gpmi-nand", "bch";

		       interrupts = <0 13 0x04>, <0 15 0x04>;

		       interrupt-names = "gpmi-dma", "bch";

		       fsl,gpmi-dma-channel = <0>;

		       status = "disabled";

		};



		timer@00a00600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x00a00600 0x20>;
@@ -495,6 +512,30 @@ 
					};

				};



				gpmi-nand {

					pinctrl_gpmi_nand_1: gpmi-nand-1 {

						fsl,pins = <1328 0xb0b1		/* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */

							    1336 0xb0b1		/* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */

							    1344 0xb0b1		/* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */

							    1352 0xb000		/* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */

							    1360 0xb0b1		/* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */

							    1365 0xb0b1		/* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */

							    1371 0xb0b1		/* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */

							    1378 0xb0b1		/* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */

							    1387 0xb0b1		/* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */

							    1393 0xb0b1		/* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */

							    1397 0xb0b1		/* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */

							    1405 0xb0b1		/* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */

							    1413 0xb0b1		/* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */

							    1421 0xb0b1		/* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */

							    1429 0xb0b1		/* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */

							    1437 0xb0b1		/* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */

							    1445 0xb0b1		/* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */

							    1453 0xb0b1		/* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */

							    1463 0x00b1>;	/* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */

					};

				};



				i2c1 {

					pinctrl_i2c1_1: i2c1grp-1 {

						fsl,pins = <137 0x4001b8b1	/* MX6Q_PAD_EIM_D21__I2C1_SCL */

arch/arm/mach-imx/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ config SOC_IMX25 
	select ARCH_MX25

	select COMMON_CLK

	select CPU_ARM926T

	select HAVE_CAN_FLEXCAN if CAN

	select ARCH_MXC_IOMUX_V3

	select MXC_AVIC
@@ -79,6 +80,7 @@ config SOC_IMX35 
	select HAVE_EPIT

	select MXC_AVIC

	select SMP_ON_UP if SMP

	select HAVE_CAN_FLEXCAN if CAN



config SOC_IMX5

	select CPU_V7
@@ -105,6 +107,7 @@ config SOC_IMX53 
	select SOC_IMX5

	select ARCH_MX5

	select ARCH_MX53

	select HAVE_CAN_FLEXCAN if CAN



if ARCH_IMX_V4_V5
@@ -826,6 +829,7 @@ config SOC_IMX6Q 
	select COMMON_CLK

	select CPU_V7

	select HAVE_ARM_SCU

	select HAVE_CAN_FLEXCAN if CAN

	select HAVE_IMX_GPC

	select HAVE_IMX_MMDC

	select HAVE_IMX_SRC

arch/arm/mach-imx/clk-imx6q.c

+9 −2
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ enum mx6q_clks { 
	esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,

	hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,

	ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,

	mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,

	mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,

	gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,

	ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,

	usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
@@ -318,7 +318,7 @@ int __init mx6q_clocks_init(void) 
	clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);



	/*                                name             parent_name          reg         shift */

	clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "ahb",               base + 0x68, 4);

	clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);

	clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);

	clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);

	clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
@@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void) 
	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);

	clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);

	clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);

	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);

	clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);

	clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);

	clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
@@ -394,6 +395,12 @@ int __init mx6q_clocks_init(void) 
	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");

	clk_register_clkdev(clk[twd], NULL, "smp_twd");

	clk_register_clkdev(clk[usboh3], NULL, "usboh3");

	clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");

	clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");

	clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");

	clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");

	clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");

	clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");

	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");

	clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");

	clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");