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Commit 3713e3f5 authored by Philippe Reynes's avatar Philippe Reynes Committed by Shawn Guo
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clk: imx35: define two clocks for rtc 



The imx35 don't define clocks for rtc.
This patch add two clocks, as needed
by the mxc rtc driver.

Signed-off-by: default avatarPhilippe Reynes <tremyfr@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 00a48fe3

drivers/clk/imx/clk-imx35.c

+5 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ static const char *std_sel[] = {"ppll", "arm"}; 
static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};



enum mx35_clks {

	ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,

	ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,

	arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,

	esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,

	spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
@@ -107,6 +107,7 @@ int __init mx35_clocks_init(void) 
	}



	clk[ckih] = imx_clk_fixed("ckih", 24000000);

	clk[ckil] = imx_clk_fixed("ckih", 32768);

	clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);

	clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
@@ -258,6 +259,9 @@ int __init mx35_clocks_init(void) 
	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");

	clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");

	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");

	/* i.mx35 has the i.mx21 type rtc */

	clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");

	clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");

	clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");

	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");

	clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");