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Commit 344f9067 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-nouveau-fixes-3.8' of... 

Merge branch 'drm-nouveau-fixes-3.8' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

Fixes the accel support for nvd9 + kepler chipsets, also fixes GK106 support.

* 'drm-nouveau-fixes-3.8' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nve0/graph: fix fuc, and enable acceleration on all known chipsets
  drm/nvc0/graph: fix fuc, and enable acceleration on GF119
  drm/nouveau/bios: cache ramcfg strap on later chipsets
  drm/nouveau/mxm: silence output if no bios data
  drm/nouveau/bios: parse/display extra version component
  drm/nouveau/bios: implement opcode 0xa9
  drm/nouveau/bios: update gpio parsing apis to match current design
  drm/nouveau: initial support for GK106
parents a49f0d1e eca15296

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc

+5 −0
Original line number Original line Diff line number Diff line
@@ -57,6 +57,11 @@ chipsets: 
.b16 #nve4_gpc_mmio_tail

.b16 #nve4_gpc_mmio_tail

.b16 #nve4_tpc_mmio_head

.b16 #nve4_tpc_mmio_head

.b16 #nve4_tpc_mmio_tail

.b16 #nve4_tpc_mmio_tail

.b8  0xe6 0 0 0

.b16 #nve4_gpc_mmio_head

.b16 #nve4_gpc_mmio_tail

.b16 #nve4_tpc_mmio_head

.b16 #nve4_tpc_mmio_tail

.b8  0 0 0 0

.b8  0 0 0 0





// GPC mmio lists

// GPC mmio lists

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h

+10 −7
Original line number Original line Diff line number Diff line
@@ -34,13 +34,16 @@ uint32_t nve0_grgpc_data[] = { 
	0x00000000,

	0x00000000,

/* 0x0064: chipsets */

/* 0x0064: chipsets */

	0x000000e4,

	0x000000e4,

	0x01040080,

	0x0110008c,

	0x014c0104,

	0x01580110,

	0x000000e7,

	0x000000e7,

	0x01040080,

	0x0110008c,

	0x014c0104,

	0x01580110,

	0x000000e6,

	0x0110008c,

	0x01580110,

	0x00000000,

	0x00000000,

/* 0x0080: nve4_gpc_mmio_head */

/* 0x008c: nve4_gpc_mmio_head */

	0x00000380,

	0x00000380,

	0x04000400,

	0x04000400,

	0x0800040c,

	0x0800040c,
@@ -74,8 +77,8 @@ uint32_t nve0_grgpc_data[] = { 
	0x14003100,

	0x14003100,

	0x000031d0,

	0x000031d0,

	0x040031e0,

	0x040031e0,

/* 0x0104: nve4_gpc_mmio_tail */

/* 0x0110: nve4_gpc_mmio_tail */

/* 0x0104: nve4_tpc_mmio_head */

/* 0x0110: nve4_tpc_mmio_head */

	0x00000048,

	0x00000048,

	0x00000064,

	0x00000064,

	0x00000088,

	0x00000088,

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc

+10 −0
Original line number Original line Diff line number Diff line
@@ -754,6 +754,16 @@ ctx_mmio_exec: 
//		on load it means: "a save preceeded this load"

//		on load it means: "a save preceeded this load"

//

//

ctx_xfer:

ctx_xfer:

	// according to mwk, some kind of wait for idle

	mov $r15 0xc00

	shl b32 $r15 6

	mov $r14 4

	iowr I[$r15 + 0x200] $r14

	ctx_xfer_idle:

		iord $r14 I[$r15 + 0x000]

		and $r14 0x2000

		bra ne #ctx_xfer_idle



	bra not $p1 #ctx_xfer_pre

	bra not $p1 #ctx_xfer_pre

	bra $p2 #ctx_xfer_pre_load

	bra $p2 #ctx_xfer_pre_load

	ctx_xfer_pre:

	ctx_xfer_pre:

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h

+74 −73
Original line number Original line Diff line number Diff line
@@ -799,79 +799,80 @@ uint32_t nvc0_grhub_code[] = { 
	0x01fa0613,

	0x01fa0613,

	0xf803f806,

	0xf803f806,

/* 0x0829: ctx_xfer */

/* 0x0829: ctx_xfer */

	0x0611f400,

	0x00f7f100,

/* 0x082f: ctx_xfer_pre */

	0x06f4b60c,

	0xf01102f4,

	0xd004e7f0,

	0x21f510f7,

/* 0x0836: ctx_xfer_idle */

	0x21f50698,

	0xfecf80fe,

	0x11f40631,

	0x00e4f100,

/* 0x083d: ctx_xfer_pre_load */

	0xf91bf420,

	0x02f7f01c,

	0xf40611f4,

	0x065721f5,

/* 0x0846: ctx_xfer_pre */

	0x066621f5,

	0xf7f01102,

	0x067821f5,

	0x9821f510,

	0x21f5f4bd,

	0x3121f506,

	0x21f50657,

	0x1c11f406,

/* 0x0856: ctx_xfer_exec */

/* 0x0854: ctx_xfer_pre_load */

	0x019806b8,

	0xf502f7f0,

	0x1427f116,

	0xf5065721,

	0x0624b604,

	0xf5066621,

	0xf10020d0,

	0xbd067821,

	0xf0a500e7,

	0x5721f5f4,

	0x1fb941e3,

	0xb821f506,

	0x8d21f402,

/* 0x086d: ctx_xfer_exec */

	0xf004e0b6,

	0x16019806,

	0x2cf001fc,

	0x041427f1,

	0x0124b602,

	0xd00624b6,

	0xf405f2fd,

	0xe7f10020,

	0x17f18d21,

	0xe3f0a500,

	0x13f04afc,

	0x021fb941,

	0x0c27f002,

	0xb68d21f4,

	0xf50012d0,

	0xfcf004e0,

	0xf1020721,

	0x022cf001,

	0xf047fc27,

	0xfd0124b6,

	0x20d00223,

	0x21f405f2,

	0x012cf000,

	0xfc17f18d,

	0xd00320b6,

	0x0213f04a,

	0xacf00012,

	0xd00c27f0,

	0x06a5f001,

	0x21f50012,

	0x9800b7f0,

	0x27f10207,

	0x0d98140c,

	0x23f047fc,

	0x00e7f015,

	0x0020d002,

	0x015c21f5,

	0xb6012cf0,

	0xf508a7f0,

	0x12d00320,

	0xf5010321,

	0x01acf000,

	0xf4020721,

	0xf006a5f0,

	0xa7f02201,

	0x0c9800b7,

	0xc921f40c,

	0x150d9814,

	0x0a1017f1,

	0xf500e7f0,

	0xf00614b6,

	0xf0015c21,

	0x12d00527,

	0x21f508a7,

/* 0x08dd: ctx_xfer_post_save_wait */

	0x21f50103,

	0x0012cf00,

	0x01f40207,

	0xf40522fd,

	0x0ca7f022,

	0x02f4fa1b,

	0xf1c921f4,

/* 0x08e9: ctx_xfer_post */

	0xb60a1017,

	0x02f7f032,

	0x27f00614,

	0x065721f5,

	0x0012d005,

	0x21f5f4bd,

/* 0x08f4: ctx_xfer_post_save_wait */

	0x21f50698,

	0xfd0012cf,

	0x21f50226,

	0x1bf40522,

	0xf4bd0666,

	0x3202f4fa,

	0x065721f5,

/* 0x0900: ctx_xfer_post */

	0x981011f4,

	0xf502f7f0,

	0x11fd8001,

	0xbd065721,

	0x070bf405,

	0x9821f5f4,

	0x07df21f5,

	0x2621f506,

/* 0x0914: ctx_xfer_no_post_mmio */

	0x6621f502,

	0x064921f5,

	0xf5f4bd06,

/* 0x0918: ctx_xfer_done */

	0xf4065721,

	0x000000f8,

	0x01981011,

	0x00000000,

	0x0511fd80,

	0x00000000,

	0xf5070bf4,

	0x00000000,

/* 0x092b: ctx_xfer_no_post_mmio */

	0x00000000,

	0xf507df21,

	0x00000000,

/* 0x092f: ctx_xfer_done */

	0xf8064921,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc

+13 −0
Original line number Original line Diff line number Diff line
@@ -44,6 +44,9 @@ chipsets: 
.b8  0xe7 0 0 0

.b8  0xe7 0 0 0

.b16 #nve4_hub_mmio_head

.b16 #nve4_hub_mmio_head

.b16 #nve4_hub_mmio_tail

.b16 #nve4_hub_mmio_tail

.b8  0xe6 0 0 0

.b16 #nve4_hub_mmio_head

.b16 #nve4_hub_mmio_tail

.b8  0 0 0 0

.b8  0 0 0 0





nve4_hub_mmio_head:

nve4_hub_mmio_head:
@@ -680,6 +683,16 @@ ctx_mmio_exec: 
//		on load it means: "a save preceeded this load"

//		on load it means: "a save preceeded this load"

//

//

ctx_xfer:

ctx_xfer:

	// according to mwk, some kind of wait for idle

	mov $r15 0xc00

	shl b32 $r15 6

	mov $r14 4

	iowr I[$r15 + 0x200] $r14

	ctx_xfer_idle:

		iord $r14 I[$r15 + 0x000]

		and $r14 0x2000

		bra ne #ctx_xfer_idle



	bra not $p1 #ctx_xfer_pre

	bra not $p1 #ctx_xfer_pre

	bra $p2 #ctx_xfer_pre_load

	bra $p2 #ctx_xfer_pre_load

	ctx_xfer_pre:

	ctx_xfer_pre: