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Commit 32231a66 authored by Al Viro's avatar Al Viro Committed by David S. Miller
Browse files

[SPARC32]: clean include/asm-sparc/irq.h 



Move stuff used only by arch/sparc/kernel/* into arch/sparc/kernel/irq.h
and into individual files in there (e.g. macros internal to sun4m_irq.c,
etc.)

Signed-off-by: default avatarAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 196bffa5

arch/sparc/kernel/irq.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -47,6 +47,8 @@ 
#include <asm/cacheflush.h>

#include <asm/cacheflush.h>

#include <asm/irq_regs.h>

#include <asm/irq_regs.h>





#include "irq.h"



#ifdef CONFIG_SMP

#ifdef CONFIG_SMP

#define SMP_NOP2 "nop; nop;\n\t"

#define SMP_NOP2 "nop; nop;\n\t"

#define SMP_NOP3 "nop; nop; nop;\n\t"

#define SMP_NOP3 "nop; nop; nop;\n\t"

arch/sparc/kernel/irq.h

0 → 100644
+48 −0
Original line number Original line Diff line number Diff line 
#include <asm/btfixup.h>



BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)

BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)

BTFIXUPDEF_CALL(void, clear_clock_irq, void)

BTFIXUPDEF_CALL(void, clear_profile_irq, int)

BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)



static inline void disable_pil_irq(unsigned int irq)

{

	BTFIXUP_CALL(disable_pil_irq)(irq);

}



static inline void enable_pil_irq(unsigned int irq)

{

	BTFIXUP_CALL(enable_pil_irq)(irq);

}



static inline void clear_clock_irq(void)

{

	BTFIXUP_CALL(clear_clock_irq)();

}



static inline void clear_profile_irq(int irq)

{

	BTFIXUP_CALL(clear_profile_irq)(irq);

}



static inline void load_profile_irq(int cpu, int limit)

{

	BTFIXUP_CALL(load_profile_irq)(cpu, limit);

}



extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);



extern void claim_ticker14(irq_handler_t irq_handler,

			   int irq,

			   unsigned int timeout);



#ifdef CONFIG_SMP

BTFIXUPDEF_CALL(void, set_cpu_int, int, int)

BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)

BTFIXUPDEF_CALL(void, set_irq_udt, int)



#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)

#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)

#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)

#endif

arch/sparc/kernel/pcic.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,7 @@ 
#include <asm/uaccess.h>

#include <asm/uaccess.h>

#include <asm/irq_regs.h>

#include <asm/irq_regs.h>





#include "irq.h"





/*

/*

 * I studied different documents and many live PROMs both from 2.30

 * I studied different documents and many live PROMs both from 2.30

arch/sparc/kernel/smp.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -33,6 +33,8 @@ 
#include <asm/tlbflush.h>

#include <asm/tlbflush.h>

#include <asm/cpudata.h>

#include <asm/cpudata.h>





#include "irq.h"



int smp_num_cpus = 1;

int smp_num_cpus = 1;

volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};

volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};

unsigned char boot_cpu_id = 0;

unsigned char boot_cpu_id = 0;

arch/sparc/kernel/sun4c_irq.c

+15 −0
Original line number Original line Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <linux/interrupt.h>

#include <linux/interrupt.h>

#include <linux/slab.h>

#include <linux/slab.h>

#include <linux/init.h>

#include <linux/init.h>

#include "irq.h"





#include <asm/ptrace.h>

#include <asm/ptrace.h>

#include <asm/processor.h>

#include <asm/processor.h>
@@ -40,6 +41,20 @@ static struct resource sun4c_timer_eb = { "sun4c_timer" }; 
static struct resource sun4c_intr_eb = { "sun4c_intr" };

static struct resource sun4c_intr_eb = { "sun4c_intr" };

#endif

#endif





/*

 * Bit field defines for the interrupt registers on various

 * Sparc machines.

 */



/* The sun4c interrupt register. */

#define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */

#define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */

#define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */

#define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */

#define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */

#define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */

#define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */



/* Pointer to the interrupt enable byte

/* Pointer to the interrupt enable byte

 *

 *

 * Dave Redman (djhr@tadpole.co.uk)

 * Dave Redman (djhr@tadpole.co.uk)