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Commit 303fd2c2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
  Blackfin: bf52x/bf54x boards: drop unused nand page size
  Blackfin: punt duplicate SPORT MMR defines
parents 6b3a7c0f 9e5610a9

arch/blackfin/include/asm/bfin_sport.h

+0 −6
Original line number Diff line number Diff line
@@ -115,12 +115,6 @@ struct sport_register { 


#endif



/* Workaround defBF*.h SPORT MMRs till they get cleansed */

#undef DTYPE_NORM

#undef SLEN

#undef SP_WOFF

#undef SP_WSIZE



/* SPORT_TCR1 Masks */

#define TSPEN		0x0001	/* TX enable */

#define ITCLK		0x0002	/* Internal TX Clock Select */

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

+0 −82
Original line number Diff line number Diff line
@@ -913,88 +913,6 @@ 
#define PH6		0x0040

#define PH7		0x0080





/* *******************  SERIAL PORT MASKS  **************************************/

/* SPORTx_TCR1 Masks															*/

#define TSPEN		0x0001		/* Transmit Enable								*/

#define ITCLK		0x0002		/* Internal Transmit Clock Select				*/

#define DTYPE_NORM	0x0004		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define TLSBIT		0x0010		/* Transmit Bit Order							*/

#define ITFS		0x0200		/* Internal Transmit Frame Sync Select			*/

#define TFSR		0x0400		/* Transmit Frame Sync Required Select			*/

#define DITFS		0x0800		/* Data-Independent Transmit Frame Sync Select	*/

#define LTFS		0x1000		/* Low Transmit Frame Sync Select				*/

#define LATFS		0x2000		/* Late Transmit Frame Sync Select				*/

#define TCKFE		0x4000		/* Clock Falling Edge Select					*/



/* SPORTx_TCR2 Masks and Macro													*/

#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/

#define TXSE		0x0100		/* TX Secondary Enable							*/

#define TSFSE		0x0200		/* Transmit Stereo Frame Sync Enable			*/

#define TRFST		0x0400		/* Left/Right Order (1 = Right Channel 1st)		*/



/* SPORTx_RCR1 Masks															*/

#define RSPEN		0x0001		/* Receive Enable 								*/

#define IRCLK		0x0002		/* Internal Receive Clock Select 				*/

#define DTYPE_NORM	0x0004		/* Data Format Normal							*/

#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/

#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/

#define RLSBIT		0x0010		/* Receive Bit Order							*/

#define IRFS		0x0200		/* Internal Receive Frame Sync Select 			*/

#define RFSR		0x0400		/* Receive Frame Sync Required Select 			*/

#define LRFS		0x1000		/* Low Receive Frame Sync Select 				*/

#define LARFS		0x2000		/* Late Receive Frame Sync Select 				*/

#define RCKFE		0x4000		/* Clock Falling Edge Select 					*/



/* SPORTx_RCR2 Masks															*/

#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)				*/

#define RXSE		0x0100		/* RX Secondary Enable							*/

#define RSFSE		0x0200		/* RX Stereo Frame Sync Enable					*/

#define RRFST		0x0400		/* Right-First Data Order 						*/



/* SPORTx_STAT Masks															*/

#define RXNE		0x0001		/* Receive FIFO Not Empty Status				*/

#define RUVF		0x0002		/* Sticky Receive Underflow Status				*/

#define ROVF		0x0004		/* Sticky Receive Overflow Status				*/

#define TXF			0x0008		/* Transmit FIFO Full Status					*/

#define TUVF		0x0010		/* Sticky Transmit Underflow Status				*/

#define TOVF		0x0020		/* Sticky Transmit Overflow Status				*/

#define TXHRE		0x0040		/* Transmit Hold Register Empty					*/



/* SPORTx_MCMC1 Macros															*/

#define SP_WOFF(x)	((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/



/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/

#define SP_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/



/* SPORTx_MCMC2 Masks															*/

#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/

#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/

#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/

#define MCDTXPE		0x0004 		/* Multichannel DMA Transmit Packing			*/

#define MCDRXPE		0x0008 		/* Multichannel DMA Receive Packing				*/

#define MCMEN		0x0010 		/* Multichannel Frame Mode Enable				*/

#define FSDR		0x0080 		/* Multichannel Frame Sync to Data Relationship	*/

#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/

#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/

#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/

#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/

#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/

#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/

#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/

#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/

#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/

#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/

#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/

#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/

#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/

#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/

#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/

#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/





/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/

/* EBIU_AMGCTL Masks																	*/

#define AMCKEN			0x0001		/* Enable CLKOUT									*/

arch/blackfin/mach-bf527/boards/cm_bf527.c

+0 −1
Original line number Diff line number Diff line
@@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = { 
};



static struct bf5xx_nand_platform bf5xx_nand_platform = {

	.page_size = NFC_PG_SIZE_256,

	.data_width = NFC_NWIDTH_8,

	.partitions = partition_info,

	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf527/boards/ezbrd.c

+0 −1
Original line number Diff line number Diff line
@@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = { 
};



static struct bf5xx_nand_platform bf5xx_nand_platform = {

	.page_size = NFC_PG_SIZE_256,

	.data_width = NFC_NWIDTH_8,

	.partitions = partition_info,

	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf527/boards/ezkit.c

+0 −1
Original line number Diff line number Diff line
@@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = { 
};



static struct bf5xx_nand_platform bf5xx_nand_platform = {

	.page_size = NFC_PG_SIZE_256,

	.data_width = NFC_NWIDTH_8,

	.partitions = partition_info,

	.nr_partitions = ARRAY_SIZE(partition_info),