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Commit 2fa86a1f authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: extend lpt_enable_clkout_dp 



Now it implements 3 different sequences from BSpec and also has
support for ULT.

v2: - Change IS_ULT checks for LPT-LP checks
    - Add check for LPT-LP + with_fdi (Ben)
    - Merge DBUFF0/GEN0 bit definitions since they're the same
      register (Ben)
    - DBUFF0 (1<<0) is Disable, not Enable

Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bc6bc15b

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -4942,7 +4942,8 @@ 
#define  SBI_SSCAUXDIV6				0x0610

#define  SBI_SSCAUXDIV6				0x0610

#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)

#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)

#define  SBI_DBUFF0				0x2a00

#define  SBI_DBUFF0				0x2a00

#define   SBI_DBUFF0_ENABLE			(1<<0)

#define  SBI_GEN0				0x1f00

#define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1<<0)





/* LPT PIXCLK_GATE */

/* LPT PIXCLK_GATE */

#define PIXCLK_GATE			0xC6020

#define PIXCLK_GATE			0xC6020

drivers/gpu/drm/i915/intel_display.c

+30 −13
Original line number Original line Diff line number Diff line
@@ -5263,11 +5263,23 @@ static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) 
	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);

	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);

}

}





/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */

/* Implements 3 different sequences from BSpec chapter "Display iCLK

static void lpt_enable_clkout_dp(struct drm_device *dev)

 * Programming" based on the parameters passed:

 * - Sequence to enable CLKOUT_DP

 * - Sequence to enable CLKOUT_DP without spread

 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O

 */

static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,

				 bool with_fdi)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t tmp;

	uint32_t reg, tmp;



	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))

		with_spread = true;

	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&

		 with_fdi, "LP PCH doesn't have FDI\n"))

		with_fdi = false;





	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->dpio_lock);
@@ -5278,17 +5290,22 @@ static void lpt_enable_clkout_dp(struct drm_device *dev) 




	udelay(24);

	udelay(24);





	if (with_spread) {

		tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

		tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

		tmp &= ~SBI_SSCCTL_PATHALT;

		tmp &= ~SBI_SSCCTL_PATHALT;

		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);





		if (with_fdi) {

			lpt_reset_fdi_mphy(dev_priv);

			lpt_reset_fdi_mphy(dev_priv);

			lpt_program_fdi_mphy(dev_priv);

			lpt_program_fdi_mphy(dev_priv);

		}

	}





	/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */

	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?

	tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);

	       SBI_GEN0 : SBI_DBUFF0;

	tmp |= SBI_DBUFF0_ENABLE;

	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);

	intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);

	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;

	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);





	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->dpio_lock);

}

}
@@ -5310,7 +5327,7 @@ static void lpt_init_pch_refclk(struct drm_device *dev) 
	if (!has_vga)

	if (!has_vga)

		return;

		return;





	lpt_enable_clkout_dp(dev);

	lpt_enable_clkout_dp(dev, true, true);

}

}





/*

/*