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Commit 2d0f2400 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (31 commits)
  drm: integer overflow in drm_mode_dirtyfb_ioctl()
  drivers/gpu/vga/vgaarb.c: add missing kfree
  drm/radeon/kms/atom: unify i2c gpio table handling
  drm/radeon/kms: fix up gpio i2c mask bits for r4xx for real
  ttm: Don't return the bo reserved on error path
  drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS
  drm/i915: Fix inconsistent backlight level during disabled
  drm, i915: Fix memory leak in i915_gem_busy_ioctl().
  drm/i915: Use DPCD value for max DP lanes.
  drm/i915: Initiate DP link training only on the lanes we'll be using
  drm/i915: Remove trailing white space
  drm/i915: Try harder during dp pattern 1 link training
  drm/i915: Make DP prepare/commit consistent with DP dpms
  drm/i915: Let panel power sequencing hardware do its job
  drm/i915: Treat PCH eDP like DP in most places
  drm/i915: Remove link_status field from intel_dp structure
  drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control
  drm/i915: Module parameters using '-1' as default must be signed type
  drm/i915: Turn on another required clock gating bit on gen6.
  drm/i915: Turn on a required 3D clock gating bit on Sandybridge.
  ...
parents b4bbb029 a5cd3351

drivers/gpu/drm/drm_crtc.c

+4 −0
Original line number Diff line number Diff line
@@ -1873,6 +1873,10 @@ int drm_mode_dirtyfb_ioctl(struct drm_device *dev, 
	}



	if (num_clips && clips_ptr) {

		if (num_clips < 0 || num_clips > DRM_MODE_FB_DIRTY_MAX_CLIPS) {

			ret = -EINVAL;

			goto out_err1;

		}

		clips = kzalloc(num_clips * sizeof(*clips), GFP_KERNEL);

		if (!clips) {

			ret = -ENOMEM;

drivers/gpu/drm/i915/i915_debugfs.c

+51 −6
Original line number Diff line number Diff line
@@ -636,11 +636,16 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	struct intel_ring_buffer *ring;

	int ret;



	ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];

	if (ring->size == 0)

		return 0;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	seq_printf(m, "Ring %s:\n", ring->name);

	seq_printf(m, "  Head :    %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);

	seq_printf(m, "  Tail :    %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
@@ -654,6 +659,8 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) 
	seq_printf(m, "  Control : %08x\n", I915_READ_CTL(ring));

	seq_printf(m, "  Start :   %08x\n", I915_READ_START(ring));



	mutex_unlock(&dev->struct_mutex);



	return 0;

}
@@ -842,7 +849,16 @@ static int i915_rstdby_delays(struct seq_file *m, void *unused) 
	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u16 crstanddelay = I915_READ16(CRSTANDVID);

	u16 crstanddelay;

	int ret;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	crstanddelay = I915_READ16(CRSTANDVID);



	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
@@ -940,7 +956,11 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 delayfreq;

	int i;

	int ret, i;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	for (i = 0; i < 16; i++) {

		delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
@@ -948,6 +968,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) 
			   (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);

	}



	mutex_unlock(&dev->struct_mutex);



	return 0;

}
@@ -962,13 +984,19 @@ static int i915_inttoext_table(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 inttoext;

	int i;

	int ret, i;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	for (i = 1; i <= 32; i++) {

		inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);

		seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);

	}



	mutex_unlock(&dev->struct_mutex);



	return 0;

}
@@ -977,9 +1005,19 @@ static int i915_drpc_info(struct seq_file *m, void *unused) 
	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 rgvmodectl = I915_READ(MEMMODECTL);

	u32 rstdbyctl = I915_READ(RSTDBYCTL);

	u16 crstandvid = I915_READ16(CRSTANDVID);

	u32 rgvmodectl, rstdbyctl;

	u16 crstandvid;

	int ret;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	rgvmodectl = I915_READ(MEMMODECTL);

	rstdbyctl = I915_READ(RSTDBYCTL);

	crstandvid = I915_READ16(CRSTANDVID);



	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?

		   "yes" : "no");
@@ -1167,9 +1205,16 @@ static int i915_gfxec(struct seq_file *m, void *unused) 
	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	int ret;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));



	mutex_unlock(&dev->struct_mutex);



	return 0;

}

drivers/gpu/drm/i915/i915_drv.c

+3 −3
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); 
MODULE_PARM_DESC(i915_enable_rc6,

		"Enable power-saving render C-state 6 (default: true)");



unsigned int i915_enable_fbc __read_mostly = -1;

int i915_enable_fbc __read_mostly = -1;

module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);

MODULE_PARM_DESC(i915_enable_fbc,

		"Enable frame buffer compression for power savings "
@@ -80,7 +80,7 @@ MODULE_PARM_DESC(lvds_downclock, 
		"Use panel (LVDS/eDP) downclocking for power savings "

		"(default: false)");



unsigned int i915_panel_use_ssc __read_mostly = -1;

int i915_panel_use_ssc __read_mostly = -1;

module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);

MODULE_PARM_DESC(lvds_use_ssc,

		"Use Spread Spectrum Clock with panels [LVDS/eDP] "
@@ -107,7 +107,7 @@ static struct drm_driver driver; 
extern int intel_agp_enabled;



#define INTEL_VGA_DEVICE(id, info) {		\

	.class = PCI_CLASS_DISPLAY_VGA << 8,	\

	.class = PCI_BASE_CLASS_DISPLAY << 16,	\

	.class_mask = 0xff0000,			\

	.vendor = 0x8086,			\

	.device = id,				\

drivers/gpu/drm/i915/i915_drv.h

+10 −9
Original line number Diff line number Diff line
@@ -126,6 +126,9 @@ struct drm_i915_master_private { 
	struct _drm_i915_sarea *sarea_priv;

};

#define I915_FENCE_REG_NONE -1

#define I915_MAX_NUM_FENCES 16

/* 16 fences + sign bit for FENCE_REG_NONE */

#define I915_MAX_NUM_FENCE_BITS 5



struct drm_i915_fence_reg {

	struct list_head lru_list;
@@ -168,7 +171,7 @@ struct drm_i915_error_state { 
	u32 instdone1;

	u32 seqno;

	u64 bbaddr;

	u64 fence[16];

	u64 fence[I915_MAX_NUM_FENCES];

	struct timeval time;

	struct drm_i915_error_object {

		int page_count;
@@ -182,7 +185,7 @@ struct drm_i915_error_state { 
		u32 gtt_offset;

		u32 read_domains;

		u32 write_domain;

		s32 fence_reg:5;

		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;

		s32 pinned:2;

		u32 tiling:2;

		u32 dirty:1;
@@ -375,7 +378,7 @@ typedef struct drm_i915_private { 
	struct notifier_block lid_notifier;



	int crt_ddc_pin;

	struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */

	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */

	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */

	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
@@ -506,7 +509,7 @@ typedef struct drm_i915_private { 
	u8 saveAR[21];

	u8 saveDACMASK;

	u8 saveCR[37];

	uint64_t saveFENCE[16];

	uint64_t saveFENCE[I915_MAX_NUM_FENCES];

	u32 saveCURACNTR;

	u32 saveCURAPOS;

	u32 saveCURABASE;
@@ -777,10 +780,8 @@ struct drm_i915_gem_object { 
	 * Fence register bits (if any) for this object.  Will be set

	 * as needed when mapped into the GTT.

	 * Protected by dev->struct_mutex.

	 *

	 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)

	 */

	signed int fence_reg:5;

	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;



	/**

	 * Advice: are the backing pages purgeable?
@@ -999,10 +1000,10 @@ extern int i915_panel_ignore_lid __read_mostly; 
extern unsigned int i915_powersave __read_mostly;

extern unsigned int i915_semaphores __read_mostly;

extern unsigned int i915_lvds_downclock __read_mostly;

extern unsigned int i915_panel_use_ssc __read_mostly;

extern int i915_panel_use_ssc __read_mostly;

extern int i915_vbt_sdvo_panel_type __read_mostly;

extern unsigned int i915_enable_rc6 __read_mostly;

extern unsigned int i915_enable_fbc __read_mostly;

extern int i915_enable_fbc __read_mostly;

extern bool i915_enable_hangcheck __read_mostly;



extern int i915_suspend(struct drm_device *dev, pm_message_t state);

drivers/gpu/drm/i915/i915_gem.c

+7 −5
Original line number Diff line number Diff line
@@ -1745,7 +1745,7 @@ static void i915_gem_reset_fences(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;



	for (i = 0; i < 16; i++) {

	for (i = 0; i < dev_priv->num_fence_regs; i++) {

		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];

		struct drm_i915_gem_object *obj = reg->obj;
@@ -3512,9 +3512,11 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, 
			 * so emit a request to do so.

			 */

			request = kzalloc(sizeof(*request), GFP_KERNEL);

			if (request)

			if (request) {

				ret = i915_add_request(obj->ring, NULL, request);

			else

				if (ret)

					kfree(request);

			} else

				ret = -ENOMEM;

		}
@@ -3613,7 +3615,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->base.read_domains = I915_GEM_DOMAIN_CPU;



	if (IS_GEN6(dev)) {

	if (IS_GEN6(dev) || IS_GEN7(dev)) {

		/* On Gen6, we can have the GPU use the LLC (the CPU

		 * cache) for about a 10% performance improvement

		 * compared to uncached.  Graphics requests other than
@@ -3877,7 +3879,7 @@ i915_gem_load(struct drm_device *dev) 
	INIT_LIST_HEAD(&dev_priv->mm.gtt_list);

	for (i = 0; i < I915_NUM_RINGS; i++)

		init_ring_lists(&dev_priv->ring[i]);

	for (i = 0; i < 16; i++)

	for (i = 0; i < I915_MAX_NUM_FENCES; i++)

		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);

	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,

			  i915_gem_retire_work_handler);