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Commit 2caa3b26 authored Feb 09, 2015 by Damien Lespiau Committed by Daniel Vetter Feb 13, 2015

drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS



Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 81e231af

drivers/gpu/drm/i915/i915_reg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -5236,6 +5236,9 @@ enum skl_disp_power_wells {
		#define HSW_NDE_RSTWRN_OPT 0x46408
		#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)

		#define FF_SLICE_CS_CHICKEN2 0x02e4
		#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)

		/* GEN7 chicken */
		#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
		# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) \| (1<<26))

drivers/gpu/drm/i915/intel_pm.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -66,11 +66,16 @@ static void skl_init_clock_gating(struct drm_device *dev)
		GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
		}

		if (INTEL_REVID(dev) <= SKL_REVID_D0)
		if (INTEL_REVID(dev) <= SKL_REVID_D0) {
		/* WaDisableHDCInvalidation:skl */
		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) \|
		BDW_DISABLE_HDC_INVALIDATION);

		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
		I915_WRITE(FF_SLICE_CS_CHICKEN2,
		I915_READ(FF_SLICE_CS_CHICKEN2) \|
		GEN9_TSG_BARRIER_ACK_DISABLE);
		}

		if (INTEL_REVID(dev) <= SKL_REVID_E0)
		/* WaDisableLSQCROPERFforOCL:skl */