Merge branch 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux into drm-next

	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \

	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o

# add asic specific block

amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \

amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o

amdgpu-y += \

	vi.o

	vi.o mxgpu_vi.o

# add GMC block

amdgpu-y += \

# add SMC block

amdgpu-y += \

	amdgpu_dpm.o \

	amdgpu_powerplay.o \

	cz_smc.o cz_dpm.o

	amdgpu_powerplay.o

# add DCE block

amdgpu-y += \

extern int amdgpu_vm_debug;

extern int amdgpu_sched_jobs;

extern int amdgpu_sched_hw_submission;

extern int amdgpu_powerplay;

extern int amdgpu_no_evict;

extern int amdgpu_direct_gma_size;

extern unsigned amdgpu_pcie_gen_cap;

	AMDGPU_THERMAL_IRQ_LAST

};

enum amdgpu_kiq_irq {

	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,

	AMDGPU_CP_KIQ_IRQ_LAST

};

int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

				  enum amd_ip_block_type block_type,

				  enum amd_clockgating_state state);

int amdgpu_set_powergating_state(struct amdgpu_device *adev,

				  enum amd_ip_block_type block_type,

				  enum amd_powergating_state state);

void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);

int amdgpu_wait_for_idle(struct amdgpu_device *adev,

			 enum amd_ip_block_type block_type);

bool amdgpu_is_idle(struct amdgpu_device *adev,

	struct list_head		list;

	struct interval_tree_node	it;

	uint64_t			offset;

	uint32_t			flags;

	uint64_t			flags;

};

/* bo virtual addresses in a specific vm */

	u32 num_queue;

};

struct amdgpu_kiq {

	u64			eop_gpu_addr;

	struct amdgpu_bo	*eop_obj;

	struct amdgpu_ring	ring;

	struct amdgpu_irq_src	irq;

};

/*

 * GPU scratch registers structures, functions & helpers

 */

struct amdgpu_scratch {

	unsigned		num_reg;

	uint32_t                reg_base;

	bool			free[32];

	uint32_t		reg[32];

	uint32_t		free_mask;

};

/*

	struct amdgpu_gca_config	config;

	struct amdgpu_rlc		rlc;

	struct amdgpu_mec		mec;

	struct amdgpu_kiq		kiq;

	struct amdgpu_scratch		scratch;

	const struct firmware		*me_fw;	/* ME firmware */

	uint32_t			me_fw_version;

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct dma_fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

		       struct amdgpu_ib *ib, struct dma_fence *last_vm_update,

		       struct amdgpu_job *job, struct dma_fence **f);

		       struct amdgpu_ib *ibs, struct amdgpu_job *job,

		       struct dma_fence **f);

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);

int amdgpu_ib_ring_tests(struct amdgpu_device *adev);

#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */

#define AMDGPU_VM_DOMAIN                    (1 << 3) /* bit set means in virtual memory context */

struct amdgpu_job {

	struct amd_sched_job    base;

	bool			use_ctx_buf;

	struct amd_sched_entity entity;

	uint32_t                srbm_soft_reset;

	bool			is_powergated;

};

/*

	struct amd_sched_entity	entity;

	uint32_t                srbm_soft_reset;

	unsigned		num_rings;

	bool			is_powergated;

};

/*

	bool (*read_disabled_bios)(struct amdgpu_device *adev);

	bool (*read_bios_from_rom)(struct amdgpu_device *adev,

				   u8 *bios, u32 length_bytes);

	void (*detect_hw_virtualization) (struct amdgpu_device *adev);

	int (*read_register)(struct amdgpu_device *adev, u32 se_num,

			     u32 sh_num, u32 reg_offset, u32 *value);

	void (*set_vga_state)(struct amdgpu_device *adev, bool state);

	/* BIOS */

	uint8_t				*bios;

	uint32_t			bios_size;

	bool				is_atom_bios;

	struct amdgpu_bo		*stollen_vga_memory;

	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];

	/* amdkfd interface */

	struct kfd_dev          *kfd;

	struct amdgpu_virtualization virtualization;

	struct amdgpu_virt	virt;

	/* link all shadow bo */

	struct list_head                shadow_list;

	ring->count_dw--;

}

static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)

{

	unsigned occupied, chunk1, chunk2;

	void *dst;

	if (ring->count_dw < count_dw) {

		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	} else {

		occupied = ring->wptr & ring->ptr_mask;

		dst = (void *)&ring->ring[occupied];

		chunk1 = ring->ptr_mask + 1 - occupied;

		chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;

		chunk2 = count_dw - chunk1;

		chunk1 <<= 2;

		chunk2 <<= 2;

		if (chunk1)

			memcpy(dst, src, chunk1);

		if (chunk2) {

			src += chunk1;

			dst = (void *)ring->ring;

			memcpy(dst, src, chunk2);

		}

		ring->wptr += count_dw;

		ring->wptr &= ring->ptr_mask;

		ring->count_dw -= count_dw;

	}

}

static inline struct amdgpu_sdma_instance *

amdgpu_get_sdma_instance(struct amdgpu_ring *ring)

{

#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))

#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_detect_hw_virtualization(adev) (adev)->asic_funcs->detect_hw_virtualization((adev))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))

#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))

#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))

#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))

#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))

#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))

#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))

#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))

			if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&

			    enc->enc_priv) {

				if (adev->is_atom_bios) {

				struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;

				if (dig->bl_dev) {

					atif->encoder_for_bl = enc;

			}

		}

	}

	}

	if (atif->functions.sbios_requests && !atif->functions.system_params) {

		/* XXX check this workraround, if sbios request function is

#define AMD_IS_VALID_VBIOS(p) ((p)[0] == 0x55 && (p)[1] == 0xAA)

#define AMD_VBIOS_LENGTH(p) ((p)[2] << 9)

/* Check if current bios is an ATOM BIOS.

 * Return true if it is ATOM BIOS. Otherwise, return false.

 */

static bool check_atom_bios(uint8_t *bios, size_t size)

{

	uint16_t tmp, bios_header_start;

	if (!bios || size < 0x49) {

		DRM_INFO("vbios mem is null or mem size is wrong\n");

		return false;

	}

	if (!AMD_IS_VALID_VBIOS(bios)) {

		DRM_INFO("BIOS signature incorrect %x %x\n", bios[0], bios[1]);

		return false;

	}

	tmp = bios[0x18] | (bios[0x19] << 8);

	if (bios[tmp + 0x14] != 0x0) {

		DRM_INFO("Not an x86 BIOS ROM\n");

		return false;

	}

	bios_header_start = bios[0x48] | (bios[0x49] << 8);

	if (!bios_header_start) {

		DRM_INFO("Can't locate bios header\n");

		return false;

	}

	tmp = bios_header_start + 4;

	if (size < tmp) {

		DRM_INFO("BIOS header is broken\n");

		return false;

	}

	if (!memcmp(bios + tmp, "ATOM", 4) ||

	    !memcmp(bios + tmp, "MOTA", 4)) {

		DRM_DEBUG("ATOMBIOS detected\n");

		return true;

	}

	return false;

}

/* If you boot an IGP board with a discrete card as the primary,

 * the IGP rom is not accessible via the rom bar as the IGP rom is

 * part of the system bios.  On boot, the system bios puts a

		return false;

	}

	if (size == 0 || !AMD_IS_VALID_VBIOS(bios)) {

		iounmap(bios);

		return false;

	}

	adev->bios = kmalloc(size, GFP_KERNEL);

	if (!adev->bios) {

		iounmap(bios);

	adev->bios_size = size;

	memcpy_fromio(adev->bios, bios, size);

	iounmap(bios);

	if (!check_atom_bios(adev->bios, size)) {

		kfree(adev->bios);

		return false;

	}

	return true;

}

bool amdgpu_read_bios(struct amdgpu_device *adev)

{

	uint8_t __iomem *bios, val[2];

	uint8_t __iomem *bios;

	size_t size;

	adev->bios = NULL;

		return false;

	}

	val[0] = readb(&bios[0]);

	val[1] = readb(&bios[1]);

	if (size == 0 || !AMD_IS_VALID_VBIOS(val)) {

		pci_unmap_rom(adev->pdev, bios);

		return false;

	}

	adev->bios = kzalloc(size, GFP_KERNEL);

	if (adev->bios == NULL) {

		pci_unmap_rom(adev->pdev, bios);

	adev->bios_size = size;

	memcpy_fromio(adev->bios, bios, size);

	pci_unmap_rom(adev->pdev, bios);

	if (!check_atom_bios(adev->bios, size)) {

		kfree(adev->bios);

		return false;

	}

	return true;

}

	adev->bios_size = len;

	/* read complete BIOS */

	return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);

	amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);

	if (!check_atom_bios(adev->bios, len)) {

		kfree(adev->bios);

		return false;

	}

	return true;

}

static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)

		return false;

	}

	if (size == 0 || !AMD_IS_VALID_VBIOS(bios)) {

	adev->bios = kzalloc(size, GFP_KERNEL);

	if (adev->bios == NULL)

		return false;

	}

	adev->bios = kmemdup(bios, size, GFP_KERNEL);

	if (adev->bios == NULL) {

	memcpy_fromio(adev->bios, bios, size);

	if (!check_atom_bios(adev->bios, size)) {

		kfree(adev->bios);

		return false;

	}

	adev->bios_size = size;

	return true;

			break;

	}

	if (i == 0 || !AMD_IS_VALID_VBIOS(adev->bios)) {

	if (!check_atom_bios(adev->bios, size)) {

		kfree(adev->bios);

		return false;

	}

#ifdef CONFIG_ACPI

static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)

{

	bool ret = false;

	struct acpi_table_header *hdr;

	acpi_size tbl_size;

	UEFI_ACPI_VFCT *vfct;

	GOP_VBIOS_CONTENT *vbios;

	VFCT_IMAGE_HEADER *vhdr;

	unsigned offset;

	if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))

		return false;

	tbl_size = hdr->length;

	if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {

		DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");

		goto out_unmap;

		return false;

	}

	vfct = (UEFI_ACPI_VFCT *)hdr;

	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {

		DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");

		goto out_unmap;

	}

	offset = vfct->VBIOSImageOffset;

	vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);

	vhdr = &vbios->VbiosHeader;

	DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",

			vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,

			vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);

	while (offset < tbl_size) {

		GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);

		VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;

	if (vhdr->PCIBus != adev->pdev->bus->number ||

	    vhdr->PCIDevice != PCI_SLOT(adev->pdev->devfn) ||

	    vhdr->PCIFunction != PCI_FUNC(adev->pdev->devfn) ||

	    vhdr->VendorID != adev->pdev->vendor ||

	    vhdr->DeviceID != adev->pdev->device) {

		DRM_INFO("ACPI VFCT table is not for this card\n");

		goto out_unmap;

		offset += sizeof(VFCT_IMAGE_HEADER);

		if (offset > tbl_size) {

			DRM_ERROR("ACPI VFCT image header truncated\n");

			return false;

		}

	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {

		offset += vhdr->ImageLength;

		if (offset > tbl_size) {

			DRM_ERROR("ACPI VFCT image truncated\n");

		goto out_unmap;

			return false;

		}

	adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);

		if (vhdr->ImageLength &&

		    vhdr->PCIBus == adev->pdev->bus->number &&

		    vhdr->PCIDevice == PCI_SLOT(adev->pdev->devfn) &&

		    vhdr->PCIFunction == PCI_FUNC(adev->pdev->devfn) &&

		    vhdr->VendorID == adev->pdev->vendor &&

		    vhdr->DeviceID == adev->pdev->device) {

			adev->bios = kmemdup(&vbios->VbiosContent,

					     vhdr->ImageLength,

					     GFP_KERNEL);

			if (!check_atom_bios(adev->bios, vhdr->ImageLength)) {

				kfree(adev->bios);

				return false;

			}

			adev->bios_size = vhdr->ImageLength;

	ret = !!adev->bios;

			return true;

		}

	}

out_unmap:

	return ret;

	DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");

	return false;

}

#else

static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)

bool amdgpu_get_bios(struct amdgpu_device *adev)

{

	bool r;

	uint16_t tmp, bios_header_start;

	if (amdgpu_atrm_get_bios(adev))

		return true;

	r = amdgpu_atrm_get_bios(adev);

	if (!r)

		r = amdgpu_acpi_vfct_bios(adev);

	if (!r)

		r = igp_read_bios_from_vram(adev);

	if (!r)

		r = amdgpu_read_bios(adev);

	if (!r) {

		r = amdgpu_read_bios_from_rom(adev);

	}

	if (!r) {

		r = amdgpu_read_disabled_bios(adev);

	}

	if (!r) {

		r = amdgpu_read_platform_bios(adev);

	}

	if (!r || adev->bios == NULL) {

		DRM_ERROR("Unable to locate a BIOS ROM\n");

		adev->bios = NULL;

		return false;

	}

	if (!AMD_IS_VALID_VBIOS(adev->bios)) {

		printk("BIOS signature incorrect %x %x\n", adev->bios[0], adev->bios[1]);

		goto free_bios;

	}

	if (amdgpu_acpi_vfct_bios(adev))

		return true;

	tmp = RBIOS16(0x18);

	if (RBIOS8(tmp + 0x14) != 0x0) {

		DRM_INFO("Not an x86 BIOS ROM, not using.\n");

		goto free_bios;

	}

	if (igp_read_bios_from_vram(adev))

		return true;

	bios_header_start = RBIOS16(0x48);

	if (!bios_header_start) {

		goto free_bios;

	}

	tmp = bios_header_start + 4;

	if (!memcmp(adev->bios + tmp, "ATOM", 4) ||

	    !memcmp(adev->bios + tmp, "MOTA", 4)) {

		adev->is_atom_bios = true;

	} else {

		adev->is_atom_bios = false;

	}

	if (amdgpu_read_bios(adev))

		return true;

	DRM_DEBUG("%sBIOS detected\n", adev->is_atom_bios ? "ATOM" : "COM");

	if (amdgpu_read_bios_from_rom(adev))

		return true;

free_bios:

	kfree(adev->bios);

	adev->bios = NULL;

	if (amdgpu_read_disabled_bios(adev))

		return true;

	if (amdgpu_read_platform_bios(adev))

		return true;

	DRM_ERROR("Unable to locate a BIOS ROM\n");

	return false;

}

	CGS_FUNC_ADEV;

	if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {

		release_firmware(adev->pm.fw);

		adev->pm.fw = NULL;

		return 0;

	}

	/* cannot release other firmware because they are not created by cgs */

	return fw_version;

}

static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,

					bool en)

{

	CGS_FUNC_ADEV;

	if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||

		adev->gfx.rlc.funcs->exit_safe_mode == NULL)

		return 0;

	if (en)

		adev->gfx.rlc.funcs->enter_safe_mode(adev);

	else

		adev->gfx.rlc.funcs->exit_safe_mode(adev);

	return 0;

}

static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,

					enum cgs_ucode_id type,

					struct cgs_firmware_info *info)

		const uint8_t *src;

		const struct smc_firmware_header_v1_0 *hdr;

		if (CGS_UCODE_ID_SMU_SK == type)

			amdgpu_cgs_rel_firmware(cgs_device, CGS_UCODE_ID_SMU);

		if (!adev->pm.fw) {

			switch (adev->asic_type) {

			case CHIP_TOPAZ:

}

static const struct cgs_ops amdgpu_cgs_ops = {

	amdgpu_cgs_gpu_mem_info,

	amdgpu_cgs_gmap_kmem,

	amdgpu_cgs_gunmap_kmem,

	amdgpu_cgs_alloc_gpu_mem,

	amdgpu_cgs_free_gpu_mem,

	amdgpu_cgs_gmap_gpu_mem,

	amdgpu_cgs_gunmap_gpu_mem,

	amdgpu_cgs_kmap_gpu_mem,

	amdgpu_cgs_kunmap_gpu_mem,

	amdgpu_cgs_read_register,

	amdgpu_cgs_write_register,

	amdgpu_cgs_read_ind_register,

	amdgpu_cgs_write_ind_register,

	amdgpu_cgs_read_pci_config_byte,

	amdgpu_cgs_read_pci_config_word,

	amdgpu_cgs_read_pci_config_dword,

	amdgpu_cgs_write_pci_config_byte,

	amdgpu_cgs_write_pci_config_word,

	amdgpu_cgs_write_pci_config_dword,

	amdgpu_cgs_get_pci_resource,

	amdgpu_cgs_atom_get_data_table,

	amdgpu_cgs_atom_get_cmd_table_revs,

	amdgpu_cgs_atom_exec_cmd_table,

	amdgpu_cgs_create_pm_request,

	amdgpu_cgs_destroy_pm_request,

	amdgpu_cgs_set_pm_request,

	amdgpu_cgs_pm_request_clock,

	amdgpu_cgs_pm_request_engine,

	amdgpu_cgs_pm_query_clock_limits,

	amdgpu_cgs_set_camera_voltages,

	amdgpu_cgs_get_firmware_info,

	amdgpu_cgs_rel_firmware,

	amdgpu_cgs_set_powergating_state,

	amdgpu_cgs_set_clockgating_state,

	amdgpu_cgs_get_active_displays_info,

	amdgpu_cgs_notify_dpm_enabled,

	amdgpu_cgs_call_acpi_method,

	amdgpu_cgs_query_system_info,

	amdgpu_cgs_is_virtualization_enabled

	.gpu_mem_info = amdgpu_cgs_gpu_mem_info,

	.gmap_kmem = amdgpu_cgs_gmap_kmem,

	.gunmap_kmem = amdgpu_cgs_gunmap_kmem,

	.alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,

	.free_gpu_mem = amdgpu_cgs_free_gpu_mem,

	.gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,

	.gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,

	.kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,

	.kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,