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Commit 28c5dcb2 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Catalin Marinas
Browse files

arm64: Rename cpuid_feature field extract routines 



Now that we have a clear understanding of the sign of a feature,
rename the routines to reflect the sign, so that it is not misused.
The cpuid_feature_extract_field() now accepts a 'sign' parameter.

Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ff96f7bc

arch/arm64/include/asm/cpufeature.h

+14 −8
Original line number Diff line number Diff line
@@ -121,15 +121,15 @@ static inline void cpus_set_cap(unsigned int num) 
}



static inline int __attribute_const__

cpuid_feature_extract_field_width(u64 features, int field, int width)

cpuid_feature_extract_signed_field_width(u64 features, int field, int width)

{

	return (s64)(features << (64 - width - field)) >> (64 - width);

}



static inline int __attribute_const__

cpuid_feature_extract_field(u64 features, int field)

cpuid_feature_extract_signed_field(u64 features, int field)

{

	return cpuid_feature_extract_field_width(features, field, 4);

	return cpuid_feature_extract_signed_field_width(features, field, 4);

}



static inline unsigned int __attribute_const__
@@ -149,17 +149,23 @@ static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp) 
	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);

}



static inline int __attribute_const__

cpuid_feature_extract_field(u64 features, int field, bool sign)

{

	return (sign) ?

		cpuid_feature_extract_signed_field(features, field) :

		cpuid_feature_extract_unsigned_field(features, field);

}



static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)

{

	return ftrp->sign ?

		cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width) :

		cpuid_feature_extract_unsigned_field_width(val, ftrp->shift, ftrp->width);

	return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);

}



static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)

{

	return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||

		cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;

	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||

		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;

}



void __init setup_cpu_features(void);

arch/arm64/include/asm/kvm_mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ static inline unsigned int kvm_get_vmid_bits(void) 
{

	int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1);



	return (cpuid_feature_extract_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;

	return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;

}



#endif /* __ASSEMBLY__ */

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -618,7 +618,7 @@ u64 read_system_reg(u32 id) 
static bool

feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)

{

	int val = cpuid_feature_extract_field(reg, entry->field_pos);

	int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);



	return val >= entry->min_field_value;

}

arch/arm64/kernel/debug-monitors.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
/* Determine debug architecture. */

u8 debug_monitors_arch(void)

{

	return cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),

	return cpuid_feature_extract_unsigned_field(read_system_reg(SYS_ID_AA64DFR0_EL1),

						ID_AA64DFR0_DEBUGVER_SHIFT);

}

arch/arm64/kvm/sys_regs.c

+1 −1
Original line number Diff line number Diff line
@@ -688,7 +688,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, 
	} else {

		u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);

		u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);

		u32 el3 = !!cpuid_feature_extract_field(pfr, ID_AA64PFR0_EL3_SHIFT);

		u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);



		p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |

			     (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |