drm/nv50-/disp: rename class members to match nvidia channel names (2832271d) · Commits · e / devices / android_kernel_teracube_mt6765

drivers/gpu/drm/nouveau/core/engine/disp/gm107.c

+8 −8

Original line number	Diff line number	Diff line
		@@ -35,8 +35,8 @@

		static struct nouveau_oclass
		gm107_disp_sclass[] = {
		{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
		{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
		{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
		{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
		{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
		{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
		{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
		@@ -44,8 +44,8 @@ gm107_disp_sclass[] = {
		};

		static struct nouveau_oclass
		gm107_disp_base_oclass[] = {
		{ GM107_DISP, &nvd0_disp_base_ofuncs },
		gm107_disp_main_oclass[] = {
		{ GM107_DISP, &nvd0_disp_main_ofuncs },
		{}
		};

		@@ -72,7 +72,7 @@ gm107_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
		if (ret)
		return ret;

		nv_engine(priv)->sclass = gm107_disp_base_oclass;
		nv_engine(priv)->sclass = gm107_disp_main_oclass;
		nv_engine(priv)->cclass = &nv50_disp_cclass;
		nv_subdev(priv)->intr = nvd0_disp_intr;
		INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
		@@ -99,9 +99,9 @@ gm107_disp_oclass = &(struct nv50_disp_impl) {
		},
		.base.vblank = &nvd0_disp_vblank_func,
		.base.outp = nvd0_disp_outp_sclass,
		.mthd.core = &nve0_disp_mast_mthd_chan,
		.mthd.base = &nvd0_disp_sync_mthd_chan,
		.mthd.core = &nve0_disp_core_mthd_chan,
		.mthd.base = &nvd0_disp_base_mthd_chan,
		.mthd.ovly = &nve0_disp_ovly_mthd_chan,
		.mthd.prev = -0x020000,
		.head.scanoutpos = nvd0_disp_base_scanoutpos,
		.head.scanoutpos = nvd0_disp_main_scanoutpos,
		}.base.base;

drivers/gpu/drm/nouveau/core/engine/disp/gm204.c

+8 −8

Original line number	Diff line number	Diff line
		@@ -35,8 +35,8 @@

		static struct nouveau_oclass
		gm204_disp_sclass[] = {
		{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
		{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
		{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
		{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
		{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
		{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
		{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
		@@ -44,8 +44,8 @@ gm204_disp_sclass[] = {
		};

		static struct nouveau_oclass
		gm204_disp_base_oclass[] = {
		{ GM204_DISP, &nvd0_disp_base_ofuncs },
		gm204_disp_main_oclass[] = {
		{ GM204_DISP, &nvd0_disp_main_ofuncs },
		{}
		};

		@@ -72,7 +72,7 @@ gm204_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
		if (ret)
		return ret;

		nv_engine(priv)->sclass = gm204_disp_base_oclass;
		nv_engine(priv)->sclass = gm204_disp_main_oclass;
		nv_engine(priv)->cclass = &nv50_disp_cclass;
		nv_subdev(priv)->intr = nvd0_disp_intr;
		INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
		@@ -106,9 +106,9 @@ gm204_disp_oclass = &(struct nv50_disp_impl) {
		},
		.base.vblank = &nvd0_disp_vblank_func,
		.base.outp = gm204_disp_outp_sclass,
		.mthd.core = &nve0_disp_mast_mthd_chan,
		.mthd.base = &nvd0_disp_sync_mthd_chan,
		.mthd.core = &nve0_disp_core_mthd_chan,
		.mthd.base = &nvd0_disp_base_mthd_chan,
		.mthd.ovly = &nve0_disp_ovly_mthd_chan,
		.mthd.prev = -0x020000,
		.head.scanoutpos = nvd0_disp_base_scanoutpos,
		.head.scanoutpos = nvd0_disp_main_scanoutpos,
		}.base.base;

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+46 −46

Original line number	Diff line number	Diff line
		@@ -374,7 +374,7 @@ nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,
		}

		const struct nv50_disp_mthd_list
		nv50_disp_mast_mthd_base = {
		nv50_disp_core_mthd_base = {
		.mthd = 0x0000,
		.addr = 0x000000,
		.data = {
		@@ -387,7 +387,7 @@ nv50_disp_mast_mthd_base = {
		};

		static const struct nv50_disp_mthd_list
		nv50_disp_mast_mthd_dac = {
		nv50_disp_core_mthd_dac = {
		.mthd = 0x0080,
		.addr = 0x000008,
		.data = {
		@@ -399,7 +399,7 @@ nv50_disp_mast_mthd_dac = {
		};

		const struct nv50_disp_mthd_list
		nv50_disp_mast_mthd_sor = {
		nv50_disp_core_mthd_sor = {
		.mthd = 0x0040,
		.addr = 0x000008,
		.data = {
		@@ -409,7 +409,7 @@ nv50_disp_mast_mthd_sor = {
		};

		const struct nv50_disp_mthd_list
		nv50_disp_mast_mthd_pior = {
		nv50_disp_core_mthd_pior = {
		.mthd = 0x0040,
		.addr = 0x000008,
		.data = {
		@@ -419,7 +419,7 @@ nv50_disp_mast_mthd_pior = {
		};

		static const struct nv50_disp_mthd_list
		nv50_disp_mast_mthd_head = {
		nv50_disp_core_mthd_head = {
		.mthd = 0x0400,
		.addr = 0x000540,
		.data = {
		@@ -466,21 +466,21 @@ nv50_disp_mast_mthd_head = {
		};

		static const struct nv50_disp_mthd_chan
		nv50_disp_mast_mthd_chan = {
		nv50_disp_core_mthd_chan = {
		.name = "Core",
		.addr = 0x000000,
		.data = {
		{ "Global", 1, &nv50_disp_mast_mthd_base },
		{ "DAC", 3, &nv50_disp_mast_mthd_dac },
		{ "SOR", 2, &nv50_disp_mast_mthd_sor },
		{ "PIOR", 3, &nv50_disp_mast_mthd_pior },
		{ "HEAD", 2, &nv50_disp_mast_mthd_head },
		{ "Global", 1, &nv50_disp_core_mthd_base },
		{ "DAC", 3, &nv50_disp_core_mthd_dac },
		{ "SOR", 2, &nv50_disp_core_mthd_sor },
		{ "PIOR", 3, &nv50_disp_core_mthd_pior },
		{ "HEAD", 2, &nv50_disp_core_mthd_head },
		{}
		}
		};

		int
		nv50_disp_mast_ctor(struct nouveau_object *parent,
		nv50_disp_core_ctor(struct nouveau_object *parent,
		struct nouveau_object *engine,
		struct nouveau_oclass oclass, void data, u32 size,
		struct nouveau_object **pobject)
		@@ -509,7 +509,7 @@ nv50_disp_mast_ctor(struct nouveau_object *parent,
		}

		static int
		nv50_disp_mast_init(struct nouveau_object *object)
		nv50_disp_core_init(struct nouveau_object *object)
		{
		struct nv50_disp_priv priv = (void )object->engine;
		struct nv50_disp_dmac mast = (void )object;
		@@ -546,7 +546,7 @@ nv50_disp_mast_init(struct nouveau_object *object)
		}

		static int
		nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
		nv50_disp_core_fini(struct nouveau_object *object, bool suspend)
		{
		struct nv50_disp_priv priv = (void )object->engine;
		struct nv50_disp_dmac mast = (void )object;
		@@ -567,11 +567,11 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
		}

		struct nv50_disp_chan_impl
		nv50_disp_mast_ofuncs = {
		.base.ctor = nv50_disp_mast_ctor,
		nv50_disp_core_ofuncs = {
		.base.ctor = nv50_disp_core_ctor,
		.base.dtor = nv50_disp_dmac_dtor,
		.base.init = nv50_disp_mast_init,
		.base.fini = nv50_disp_mast_fini,
		.base.init = nv50_disp_core_init,
		.base.fini = nv50_disp_core_fini,
		.base.map = nv50_disp_chan_map,
		.base.ntfy = nv50_disp_chan_ntfy,
		.base.rd32 = nv50_disp_chan_rd32,
		@@ -586,7 +586,7 @@ nv50_disp_mast_ofuncs = {
		******************************************************************************/

		static const struct nv50_disp_mthd_list
		nv50_disp_sync_mthd_base = {
		nv50_disp_base_mthd_base = {
		.mthd = 0x0000,
		.addr = 0x000000,
		.data = {
		@@ -611,7 +611,7 @@ nv50_disp_sync_mthd_base = {
		};

		const struct nv50_disp_mthd_list
		nv50_disp_sync_mthd_image = {
		nv50_disp_base_mthd_image = {
		.mthd = 0x0400,
		.addr = 0x000000,
		.data = {
		@@ -625,18 +625,18 @@ nv50_disp_sync_mthd_image = {
		};

		static const struct nv50_disp_mthd_chan
		nv50_disp_sync_mthd_chan = {
		nv50_disp_base_mthd_chan = {
		.name = "Base",
		.addr = 0x000540,
		.data = {
		{ "Global", 1, &nv50_disp_sync_mthd_base },
		{ "Image", 2, &nv50_disp_sync_mthd_image },
		{ "Global", 1, &nv50_disp_base_mthd_base },
		{ "Image", 2, &nv50_disp_base_mthd_image },
		{}
		}
		};

		int
		nv50_disp_sync_ctor(struct nouveau_object *parent,
		nv50_disp_base_ctor(struct nouveau_object *parent,
		struct nouveau_object *engine,
		struct nouveau_oclass oclass, void data, u32 size,
		struct nouveau_object **pobject)
		@@ -669,8 +669,8 @@ nv50_disp_sync_ctor(struct nouveau_object *parent,
		}

		struct nv50_disp_chan_impl
		nv50_disp_sync_ofuncs = {
		.base.ctor = nv50_disp_sync_ctor,
		nv50_disp_base_ofuncs = {
		.base.ctor = nv50_disp_base_ctor,
		.base.dtor = nv50_disp_dmac_dtor,
		.base.init = nv50_disp_dmac_init,
		.base.fini = nv50_disp_dmac_fini,
		@@ -942,7 +942,7 @@ nv50_disp_curs_ofuncs = {
		******************************************************************************/

		int
		nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
		nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
		{
		const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
		const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
		@@ -974,7 +974,7 @@ nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
		}

		int
		nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
		nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
		void *data, u32 size)
		{
		const struct nv50_disp_impl impl = (void )nv_oclass(object->engine);
		@@ -1098,7 +1098,7 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
		}

		int
		nv50_disp_base_ctor(struct nouveau_object *parent,
		nv50_disp_main_ctor(struct nouveau_object *parent,
		struct nouveau_object *engine,
		struct nouveau_oclass oclass, void data, u32 size,
		struct nouveau_object **pobject)
		@@ -1118,7 +1118,7 @@ nv50_disp_base_ctor(struct nouveau_object *parent,
		}

		void
		nv50_disp_base_dtor(struct nouveau_object *object)
		nv50_disp_main_dtor(struct nouveau_object *object)
		{
		struct nv50_disp_base base = (void )object;
		nouveau_ramht_ref(NULL, &base->ramht);
		@@ -1126,7 +1126,7 @@ nv50_disp_base_dtor(struct nouveau_object *object)
		}

		static int
		nv50_disp_base_init(struct nouveau_object *object)
		nv50_disp_main_init(struct nouveau_object *object)
		{
		struct nv50_disp_priv priv = (void )object->engine;
		struct nv50_disp_base base = (void )object;
		@@ -1194,7 +1194,7 @@ nv50_disp_base_init(struct nouveau_object *object)
		}

		static int
		nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
		nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
		{
		struct nv50_disp_priv priv = (void )object->engine;
		struct nv50_disp_base base = (void )object;
		@@ -1207,25 +1207,25 @@ nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
		}

		struct nouveau_ofuncs
		nv50_disp_base_ofuncs = {
		.ctor = nv50_disp_base_ctor,
		.dtor = nv50_disp_base_dtor,
		.init = nv50_disp_base_init,
		.fini = nv50_disp_base_fini,
		.mthd = nv50_disp_base_mthd,
		nv50_disp_main_ofuncs = {
		.ctor = nv50_disp_main_ctor,
		.dtor = nv50_disp_main_dtor,
		.init = nv50_disp_main_init,
		.fini = nv50_disp_main_fini,
		.mthd = nv50_disp_main_mthd,
		.ntfy = nouveau_disp_ntfy,
		};

		static struct nouveau_oclass
		nv50_disp_base_oclass[] = {
		{ NV50_DISP, &nv50_disp_base_ofuncs },
		nv50_disp_main_oclass[] = {
		{ NV50_DISP, &nv50_disp_main_ofuncs },
		{}
		};

		static struct nouveau_oclass
		nv50_disp_sclass[] = {
		{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
		{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
		{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
		{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
		{ NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
		{ NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
		{ NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
		@@ -1974,7 +1974,7 @@ nv50_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
		if (ret)
		return ret;

		nv_engine(priv)->sclass = nv50_disp_base_oclass;
		nv_engine(priv)->sclass = nv50_disp_main_oclass;
		nv_engine(priv)->cclass = &nv50_disp_cclass;
		nv_subdev(priv)->intr = nv50_disp_intr;
		INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
		@@ -2007,9 +2007,9 @@ nv50_disp_oclass = &(struct nv50_disp_impl) {
		},
		.base.vblank = &nv50_disp_vblank_func,
		.base.outp = nv50_disp_outp_sclass,
		.mthd.core = &nv50_disp_mast_mthd_chan,
		.mthd.base = &nv50_disp_sync_mthd_chan,
		.mthd.core = &nv50_disp_core_mthd_chan,
		.mthd.base = &nv50_disp_base_mthd_chan,
		.mthd.ovly = &nv50_disp_ovly_mthd_chan,
		.mthd.prev = 0x000004,
		.head.scanoutpos = nv50_disp_base_scanoutpos,
		.head.scanoutpos = nv50_disp_main_scanoutpos,
		}.base.base;

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+29 −29

Original line number	Diff line number	Diff line
		@@ -64,10 +64,10 @@ struct nv50_disp_impl {
		} head;
		};

		int nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0);
		int nv50_disp_base_mthd(struct nouveau_object , u32, void , u32);
		int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
		int nv50_disp_main_mthd(struct nouveau_object , u32, void , u32);

		int nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0);
		int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0);

		int nv50_dac_power(NV50_DISP_MTHD_V1);
		int nv50_dac_sense(NV50_DISP_MTHD_V1);
		@@ -170,18 +170,18 @@ struct nv50_disp_mthd_chan {
		} data[];
		};

		extern struct nv50_disp_chan_impl nv50_disp_mast_ofuncs;
		int nv50_disp_mast_ctor(struct nouveau_object , struct nouveau_object ,
		extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
		int nv50_disp_core_ctor(struct nouveau_object , struct nouveau_object ,
		struct nouveau_oclass , void , u32,
		struct nouveau_object **);
		extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base;
		extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor;
		extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior;
		extern struct nv50_disp_chan_impl nv50_disp_sync_ofuncs;
		int nv50_disp_sync_ctor(struct nouveau_object , struct nouveau_object ,
		extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
		extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
		extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
		extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
		int nv50_disp_base_ctor(struct nouveau_object , struct nouveau_object ,
		struct nouveau_oclass , void , u32,
		struct nouveau_object **);
		extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image;
		extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
		extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
		int nv50_disp_ovly_ctor(struct nouveau_object , struct nouveau_object ,
		struct nouveau_oclass , void , u32,
		@@ -195,12 +195,12 @@ extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
		int nv50_disp_curs_ctor(struct nouveau_object , struct nouveau_object ,
		struct nouveau_oclass , void , u32,
		struct nouveau_object **);
		extern struct nouveau_ofuncs nv50_disp_base_ofuncs;
		int nv50_disp_base_ctor(struct nouveau_object , struct nouveau_object ,
		extern struct nouveau_ofuncs nv50_disp_main_ofuncs;
		int nv50_disp_main_ctor(struct nouveau_object , struct nouveau_object ,
		struct nouveau_oclass , void , u32,
		struct nouveau_object **);
		void nv50_disp_base_dtor(struct nouveau_object *);
		extern struct nouveau_omthds nv50_disp_base_omthds[];
		void nv50_disp_main_dtor(struct nouveau_object *);
		extern struct nouveau_omthds nv50_disp_main_omthds[];
		extern struct nouveau_oclass nv50_disp_cclass;
		void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
		const struct nv50_disp_mthd_chan *);
		@@ -208,31 +208,31 @@ void nv50_disp_intr_supervisor(struct work_struct *);
		void nv50_disp_intr(struct nouveau_subdev *);
		extern const struct nvkm_event_func nv50_disp_vblank_func;

		extern const struct nv50_disp_mthd_chan nv84_disp_mast_mthd_chan;
		extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_dac;
		extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_head;
		extern const struct nv50_disp_mthd_chan nv84_disp_sync_mthd_chan;
		extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan;
		extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac;
		extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head;
		extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan;
		extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;

		extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan;
		extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan;

		extern struct nv50_disp_chan_impl nvd0_disp_mast_ofuncs;
		extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base;
		extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac;
		extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor;
		extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior;
		extern struct nv50_disp_chan_impl nvd0_disp_sync_ofuncs;
		extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs;
		extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base;
		extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac;
		extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor;
		extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior;
		extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs;
		extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
		extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan;
		extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan;
		extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
		extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
		extern struct nouveau_ofuncs nvd0_disp_base_ofuncs;
		extern struct nouveau_ofuncs nvd0_disp_main_ofuncs;
		extern struct nouveau_oclass nvd0_disp_cclass;
		void nvd0_disp_intr_supervisor(struct work_struct *);
		void nvd0_disp_intr(struct nouveau_subdev *);
		extern const struct nvkm_event_func nvd0_disp_vblank_func;

		extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan;
		extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan;
		extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;

		extern struct nvkm_output_dp_impl nv50_pior_dp_impl;

drivers/gpu/drm/nouveau/core/engine/disp/nv84.c

+20 −20

Original line number	Diff line number	Diff line
		@@ -34,7 +34,7 @@
		******************************************************************************/

		const struct nv50_disp_mthd_list
		nv84_disp_mast_mthd_dac = {
		nv84_disp_core_mthd_dac = {
		.mthd = 0x0080,
		.addr = 0x000008,
		.data = {
		@@ -46,7 +46,7 @@ nv84_disp_mast_mthd_dac = {
		};

		const struct nv50_disp_mthd_list
		nv84_disp_mast_mthd_head = {
		nv84_disp_core_mthd_head = {
		.mthd = 0x0400,
		.addr = 0x000540,
		.data = {
		@@ -98,15 +98,15 @@ nv84_disp_mast_mthd_head = {
		};

		const struct nv50_disp_mthd_chan
		nv84_disp_mast_mthd_chan = {
		nv84_disp_core_mthd_chan = {
		.name = "Core",
		.addr = 0x000000,
		.data = {
		{ "Global", 1, &nv50_disp_mast_mthd_base },
		{ "DAC", 3, &nv84_disp_mast_mthd_dac },
		{ "SOR", 2, &nv50_disp_mast_mthd_sor },
		{ "PIOR", 3, &nv50_disp_mast_mthd_pior },
		{ "HEAD", 2, &nv84_disp_mast_mthd_head },
		{ "Global", 1, &nv50_disp_core_mthd_base },
		{ "DAC", 3, &nv84_disp_core_mthd_dac },
		{ "SOR", 2, &nv50_disp_core_mthd_sor },
		{ "PIOR", 3, &nv50_disp_core_mthd_pior },
		{ "HEAD", 2, &nv84_disp_core_mthd_head },
		{}
		}
		};
		@@ -116,7 +116,7 @@ nv84_disp_mast_mthd_chan = {
		******************************************************************************/

		static const struct nv50_disp_mthd_list
		nv84_disp_sync_mthd_base = {
		nv84_disp_base_mthd_base = {
		.mthd = 0x0000,
		.addr = 0x000000,
		.data = {
		@@ -146,12 +146,12 @@ nv84_disp_sync_mthd_base = {
		};

		const struct nv50_disp_mthd_chan
		nv84_disp_sync_mthd_chan = {
		nv84_disp_base_mthd_chan = {
		.name = "Base",
		.addr = 0x000540,
		.data = {
		{ "Global", 1, &nv84_disp_sync_mthd_base },
		{ "Image", 2, &nv50_disp_sync_mthd_image },
		{ "Global", 1, &nv84_disp_base_mthd_base },
		{ "Image", 2, &nv50_disp_base_mthd_image },
		{}
		}
		};
		@@ -204,8 +204,8 @@ nv84_disp_ovly_mthd_chan = {

		static struct nouveau_oclass
		nv84_disp_sclass[] = {
		{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
		{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
		{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
		{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
		{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
		{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
		{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
		@@ -213,8 +213,8 @@ nv84_disp_sclass[] = {
		};

		static struct nouveau_oclass
		nv84_disp_base_oclass[] = {
		{ G82_DISP, &nv50_disp_base_ofuncs },
		nv84_disp_main_oclass[] = {
		{ G82_DISP, &nv50_disp_main_ofuncs },
		{}
		};

		@@ -240,7 +240,7 @@ nv84_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
		if (ret)
		return ret;

		nv_engine(priv)->sclass = nv84_disp_base_oclass;
		nv_engine(priv)->sclass = nv84_disp_main_oclass;
		nv_engine(priv)->cclass = &nv50_disp_cclass;
		nv_subdev(priv)->intr = nv50_disp_intr;
		INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
		@@ -268,9 +268,9 @@ nv84_disp_oclass = &(struct nv50_disp_impl) {
		},
		.base.vblank = &nv50_disp_vblank_func,
		.base.outp = nv50_disp_outp_sclass,
		.mthd.core = &nv84_disp_mast_mthd_chan,
		.mthd.base = &nv84_disp_sync_mthd_chan,
		.mthd.core = &nv84_disp_core_mthd_chan,
		.mthd.base = &nv84_disp_base_mthd_chan,
		.mthd.ovly = &nv84_disp_ovly_mthd_chan,
		.mthd.prev = 0x000004,
		.head.scanoutpos = nv50_disp_base_scanoutpos,
		.head.scanoutpos = nv50_disp_main_scanoutpos,
		}.base.base;