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Commit 278978e9 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Bartlomiej Zolnierkiewicz
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hpt366: disallow Ultra133 for HPT374 



Eliminate UltraATA/133 support for HPT374 -- the chip isn't capable of this mode
according to the manual, and doesn't even seem to tolerate 66 MHz DPLL clock...

Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Geller Sandor <wildy@petra.hos.u-szeged.hu>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
parent ea307596

drivers/ide/pci/hpt366.c

+4 −4
Original line number Original line Diff line number Diff line 
/*

/*

 * linux/drivers/ide/pci/hpt366.c		Version 1.03	May 4, 2007

 * linux/drivers/ide/pci/hpt366.c		Version 1.04	Jun 4, 2007

 *

 *

 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>

 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>

 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.

 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
@@ -106,7 +106,8 @@ 
 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL

 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL

 *   frequency

 *   frequency

 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on

 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on

 *   anything  newer than HPT370/A

 *   anything  newer than HPT370/A (except HPT374 that is not capable of this

 *   mode according to the manual)

 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),

 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),

 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;

 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;

 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining

 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
@@ -365,7 +366,6 @@ static u32 sixty_six_base_hpt37x[] = { 
};

};





#define HPT366_DEBUG_DRIVE_INFO		0

#define HPT366_DEBUG_DRIVE_INFO		0

#define HPT374_ALLOW_ATA133_6		1

#define HPT371_ALLOW_ATA133_6		1

#define HPT371_ALLOW_ATA133_6		1

#define HPT302_ALLOW_ATA133_6		1

#define HPT302_ALLOW_ATA133_6		1

#define HPT372_ALLOW_ATA133_6		1

#define HPT372_ALLOW_ATA133_6		1
@@ -450,7 +450,7 @@ static struct hpt_info hpt370a __devinitdata = { 




static struct hpt_info hpt374 __devinitdata = {

static struct hpt_info hpt374 __devinitdata = {

	.chip_type	= HPT374,

	.chip_type	= HPT374,

	.max_mode	= HPT374_ALLOW_ATA133_6 ? 4 : 3,

	.max_mode	= 3,

	.dpll_clk	= 48,

	.dpll_clk	= 48,

	.settings	= hpt37x_settings

	.settings	= hpt37x_settings

};

};