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Commit 2435cdd0 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Lorenzo Pieralisi
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PCI: armada8k: Fix clock resource by adding a register clock 



On Armada 7K/8K we need to explicitly enable the register clock. This
clock is optional because not all the SoCs using this IP need it but at
least for Armada 7K/8K it is actually mandatory.

The binding documentation is updated accordingly.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 5dcd7f15

Documentation/devicetree/bindings/pci/pci-armada8k.txt

+4 −1
Original line number Diff line number Diff line
@@ -12,7 +12,10 @@ Required properties: 
   - "ctrl" for the control register region

   - "config" for the config space region

- interrupts: Interrupt specifier for the PCIe controler

- clocks: reference to the PCIe controller clock

- clocks: reference to the PCIe controller clocks

- clock-names: mandatory if there is a second clock, in this case the

   name must be "core" for the first clock and "reg" for the second

   one



Example:

drivers/pci/dwc/pcie-armada8k.c

+16 −2
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
struct armada8k_pcie {

	struct dw_pcie *pci;

	struct clk *clk;

	struct clk *clk_reg;

};



#define PCIE_VENDOR_REGS_OFFSET		0x8000
@@ -229,23 +230,36 @@ static int armada8k_pcie_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	pcie->clk_reg = devm_clk_get(dev, "reg");

	if (pcie->clk_reg == ERR_PTR(-EPROBE_DEFER)) {

		ret = -EPROBE_DEFER;

		goto fail;

	}

	if (!IS_ERR(pcie->clk_reg)) {

		ret = clk_prepare_enable(pcie->clk_reg);

		if (ret)

			goto fail_clkreg;

	}



	/* Get the dw-pcie unit configuration/control registers base. */

	base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");

	pci->dbi_base = devm_pci_remap_cfg_resource(dev, base);

	if (IS_ERR(pci->dbi_base)) {

		dev_err(dev, "couldn't remap regs base %p\n", base);

		ret = PTR_ERR(pci->dbi_base);

		goto fail;

		goto fail_clkreg;

	}



	platform_set_drvdata(pdev, pcie);



	ret = armada8k_add_pcie_port(pcie, pdev);

	if (ret)

		goto fail;

		goto fail_clkreg;



	return 0;



fail_clkreg:

	clk_disable_unprepare(pcie->clk_reg);

fail:

	clk_disable_unprepare(pcie->clk);